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Section 22. 12-bit High-Speed Successive Approximation

This section of the manual contains the following major topics:

22.1 Introduction .................................................................................................................. 22-2

22.2 Control Registers ......................................................................................................... 22-6

22.3 ADC Operation........................................................................................................... 22-61

22.4 ADC Module Configuration ........................................................................................ 22-65

22.5 Additional ADC Functions .......................................................................................... 22-85

22.6 Interrupts.................................................................................................................. 22-108

22.7 Operation During Power-Saving Modes .................................................................. 22-114

22.8 Effects of Reset........................................................................................................ 22-116

22.9 Transfer Function..................................................................................................... 22-116

22.10 ADC Sampling Requirements.................................................................................. 22-117

22.11 Connection Considerations...................................................................................... 22-117

22.12 Related Application Notes........................................................................................ 22-118

22.13 Revision History ....................................................................................................... 22-119

PIC32 Family Reference Manual

22.1 INTRODUCTION

The PIC32 12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital

Converter (ADC) includes the following features:

• 12-bit resolution

• Up to eight ADC modules with dedicated Sample and Hold (S&H) circuits (see Note 1)

• Two dedicated ADC modules can be combined in Turbo mode to provide double

conversion rate

• Single-ended and/or differential inputs

• Can operate during Sleep mode

• Supports touch sense applications

• Up to six digital comparators

• Up to six digital filters supporting two modes:

- Oversampling mode

- Averaging mode

• FIFO and DMA engine for dedicated ADC modules (see Note 2)

• Early interrupt generation resulting in faster processing of converted data

• Designed for motor control, power conversion, and general purpose applications

The dedicated ADC modules use a single input (or its alternate) and is intended for high-speed

and precise sampling of time-sensitive or transient inputs, whereas the shared ADC module

incorporates a multiplexer on the input to facilitate a larger group of inputs, with slower sampling,

and provides flexible automated scanning option through the input scan logic.

For each ADC module, the analog inputs are connected to the S&H capacitor. The clock,

sampling time, and output data resolution for each ADC module can be set independently. The

ADC module performs the conversion of the input analog signal based on the configurations set

in the registers. When conversion is complete, the final result is stored in the result buffer for the

specific analog input and is passed to the digital filter and digital comparator if configured to use

data from this particular sample.

A simplified block diagram of the ADC module is illustrated in Figure 22-1.

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device, this manual section may not apply to all

PIC32 devices.

Please refer to the note at the beginning of the “ADC” chapter in the current device

data sheet to check whether this document supports the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

Note 1: Depending on the device, the 12-bit High-Speed SAR ADC has up to seven

dedicated ADC modules and one shared ADC module. Throughout this chapter,

the diagrams and code examples refer to a device with seven dedicated ADC

modules (ADC0-ADC6) and one shared ADC (ADC7). Please consult the “ADC”

chapter in the specific device data sheet to determine which ADC modules are

available for your device.

2: This feature is not available on all devices. Refer to the “ADC” chapter in the

specific device data sheet to determine availability.

3: Prior to enabling the ADC module, the user application must copy the ADC

calibration data (DEVADCx) from the Configuration memory into the ADC

Configuration registers (ADC0CFG-ADC7CFG). Refer to the “ADC” chapter in the

specific device data sheet for more information.

Section 22. 12-bit High-Speed SAR ADC

Figure 22-1: ADC Block Diagram

Note: The number of ADC modules, analog inputs, ANa, ANb, ANc, and ANd, and the FIFO and DMA features

are shown as an example. Refer to the “ADC” chapter in the specific device data sheet to determine the

actual ANx selections, ADC module availability, and the specific FIFO and DMA features.

ADC0

ADC7

REF

+ V

REF

VREFSEL<2:0>

REFH

REFL

ADCSEL<1:0>

CONCLKDIV<5:0>

FRC PBCLK

ADCDIV<6:0>

(ADCxTIME<22:16>)

ADCDIV<6:0>

(ADCCON2<6:0>)

AD0

-T

AD6

AD7

ADDATA0

…...

ADDATA63

(Dedicated

ADC)

(Dedicated

ADC)

FIFO

DMA

Digital Filter

Digital Comparator Interrupt/Event

Capacitive Voltage

Divider (CVD) Interrupt/Event

Triggers,

Turbo Channel,

Scan Control Logic

Trigger

Status and Control

Registers

ADC6

SH0ALT<1:0>

(ADCTRGMODE<17:16>)

ANx

REFL

DIFFx<1>

(ADCIMCONx<x>)

ANa

AN1

REFL

DIFF1<1>

(ADCIMCON1<3>)

SH6ALT<1:0>

(ADCTRGMODE<29:28>)

ANx

REFL

DIFFx<1>

(ADCIMCONx<x>)

AN49

CTMU

BAT

AN48

AN7

CVD

Capacitor

CLK

ANb

ANc

ANd

ANb

ANc

ANd

SYSTEMBUS

ANa

Interrupt

Data

PIC32 Family Reference Manual

Figure 22-2: FIFO Block Diagram

FEN

(ADCFSTAT<31>

FIFO

(Depth Device Dependent)

ADCFIFO DATA<31:0>

ADCID<2:0>

ADCFSTAT<2:0> ADCx ID

ADCx ID Converted Data

ADC6

ADC6EN

(ADCFSTAT<30>)

ADC5

ADC5EN

(ADCFSTAT<29>)

ADC0

ADC0EN

(ADCFSTAT<24>)

If data

available in

FIFO

FRDY

ADCFSTAT<22>

FIEN

(ADCFSTAT<23>

Interrupt

FCNT<7:0>

ADCFSTAT<15:8>

(Number of data in FIFO)

Note: The number of ADC modules, analog inputs, ANa, ANb, ANc, and ANd, and the FIFO and DMA features

are shown as an example. Refer to the “ADC” chapter in the specific device data sheet to determine the

actual ANx selections, ADC module availability, and the specific FIFO and DMA features.

Section 22. 12-bit High-Speed SAR ADC

Figure 22-3: DMA Block Diagram

DMAGEN

(ADCDMASTAT<31>)

ADC6

DMAEN

(ADC6TIME<23>)

ADC5

ADC0

DMAEN

(ADC5TIME<23>)

DMAEN

(ADC0TIME<23>)

Buffer A (ADC0)

Buffer B (ADC0)

Buffer A (ADC1)

Buffer B (ADC1)

Buffer A (ADC6)

Buffer B (ADC6)

DMABL<2:0>

Buffer

Full?

RAF0

(ADCDMASTAT<0>)

RAFIEN0

(ADCDMASTAT<8>)

Interrupt

Buffer

Full?

RBF6

(ADCDMASTAT<22>)

RBFIEN6

(ADCDMASTAT<30>)

Interrupt

Data Count for Buffer-A

(ADC0)

Data Count for Buffer-B

(ADC0)

Data Count for Buffer-A

(ADC1)

Data Count for Buffer-B

(ADC1)

Data Count for Buffer-A

(ADC6)

Data Count for Buffer-B

(ADC6)

DMABADDR<31:0>

CNTBADDR<31:0>

CNTBADDR<31:0> + 1

CNTBADDR<31:0> + 2

CNTBADDR<31:0> + 3

Note: The number of ADC modules, analog inputs, ANa, ANb, ANc, and ANd, and the FIFO and DMA features

are shown as an example. Refer to the “ADC” chapter in the specific device data sheet to determine the

actual ANx selections, ADC module availability, and the specific FIFO and DMA features.

PIC32 Family Reference Manual

22.2 CONTROL REGISTERS

The PIC32 12-bit High-Speed SAR ADC module has the following Special Function Registers

(SFRs):

•ADCCON1: ADC Control Register 1

This register controls the basic operation of all ADC modules, including behavior in Sleep

and Idle modes, and data formatting. This register also specifies the vector shift amounts for

the Interrupt Controller. Additional ADCCON1 functions include controlling the Turbo feature

of the ADC, the RAM buffer length in DMA mode, and Capacitive Voltage Division (CVD).

•ADCCON2: ADC Control Register 2

This register controls the reference selection for all ADC modules, the sample time for the

shared ADC module, interrupt enable for reference, early interrupt selection, and clock

division selection for the shared ADC.

•ADCCON3: ADC Control Register 3

This register enables ADC clock selection, enables/disables the digital feature for the

dedicated and shared ADC modules and controls the manual (software) sampling and

conversion.

•ADCTRGMODE: ADC Triggering Mode for Dedicated ADC Register

This register has selections for alternate analog inputs and includes trigger settings for the

dedicated ADC modules.

•ADCIMCON1: ADC Input Mode Control Register 1 through

ADCIMCON4: ADC Input Mode Control Register 4

These registers enable the user to select between single-ended and differential operation

as well as select between signed and unsigned data format.

•ADCGIRQEN1: ADC Global Interrupt Enable Register 1 and

ADCGIRQEN2: ADC Global Interrupt Enable Register 2

These registers specify which of the individual input conversion interrupts can generate the

global ADC interrupt.

•ADCCSS1: ADC Common Scan Select Register 1 and

ADCCSS2: ADC Common Scan Select Register 2

These registers specify the analog inputs to be scanned by the common scan trigger.

•ADCDSTAT1: ADC Data Ready Status Register 1 and

ADCDSTAT2: ADC Data Ready Status Register 2

These registers contain the interrupt status of the individual analog input conversions. Each

bit represents the data-ready status for its associated conversion result.

•ADCCMPENx: ADC Digital Comparator ‘x’ Enable Register (‘x’ = 1 through 6)

These registers select which analog input conversion results will be processed by the digital

comparator.

•ADCCMPx: ADC Digital Comparator ‘x’ Limit Value Register (‘x’ = 1 through 6)

These registers contain the high and low digital comparison values for use by the digital

comparator.

•ADCFLTRx: ADC Digital Filter ‘x’ Register (‘x’ = 1 through 6)

These registers provide control and status bits for the oversampling filter accumulator, and

also includes the 16-bit filter output data.

•ADCTRG1: ADC Trigger Source 1Register

This register controls the trigger source selection for AN0 through AN3 analog inputs.

•ADCTRG2: ADC Trigger Source 2 Register

This register controls the trigger source selection for AN4 through AN7 analog inputs.

•ADCTRG3: ADC Trigger Source 3 Register

This register controls the trigger source selection for AN8 through AN11 analog inputs.

•ADCTRG4: ADC Trigger Source 4 Register

This register controls the trigger source selection for AN12 through AN15 analog inputs.

•ADCTRG5: ADC Trigger Source 5 Register

This register controls the trigger source selection for AN16 through AN19 analog inputs.

Section 22. 12-bit High-Speed SAR ADC

•ADCTRG6: ADC Trigger Source 6 Register

This register controls the trigger source selection for AN20 through AN23 analog inputs.

•ADCTRG7: ADC Trigger Source 7 Register

This register controls the trigger source selection for AN24 through AN27 analog inputs.

•ADCTRG8: ADC Trigger Source 8 Register

This register controls the trigger source selection for AN28 through AN31 analog inputs.

•ADCCMPCON1: ADC Digital Comparator 1 Control Register

This register controls the operation of Digital Comparator 1, including the generation of inter-

rupts, comparison criteria to be used, and provides status when a comparator event occurs.

Additionally, this register provides the output data of CVD.

•ADCCMPCONx: ADC Digital Comparator ‘x’ Control Register (‘x’ = 2 through 6)

These registers control the operation of Digital Comparators 2 through 6, including the

generation of interrupts and the comparison criteria to be used. This register also provides

status when a comparator event occurs.

•ADCFSTAT: ADC FIFO Status Register

This register specifies the status of the dedicated ADC module FIFO.

•ADCFIFO: ADC FIFO Data Register

This register specifies the output value of the dedicated ADC module FIFO.

•ADCBASE: ADC Base Register

These registers specify the base address of the user ADC Interrupt Service Routine (ISR)

jump table.

•ADCDMASTAT: ADC DMA Status Register

This register contains the DMA status bits.

•ADCCNTB: ADC Sample Count Base Address Register

This register contains the base address of the sample count in RAM. In addition to storying

the converted data of each dedicated ADC module in RAM, DMA also stores the converted

sample count.

•ADCDMAB: ADC DMA Base Address Register

This register contains the base address of RAM for the DMA engine.

•ADCTRGSNS: ADC Trigger Level/Edge Sensitivity Register

This register contains the setting for trigger level for each ADC analog input.

•ADCxTIME: Dedicated ADCx Timing Register ‘x’ (‘x’ = 0 through 6)

These registers contains the time and clock setting for dedicated analog input.

•ADCEIEN1: ADC Early Interrupt Enable Register 1 and

ADCEIEN2: ADC Early Interrupt Enable Register 2

These registers contains bits to enable or disable early interrupt for individual analog inputs.

•ADCEISTAT1: ADC Early Interrupt Status Register 1 and

ADCEISTAT2: ADC Early Interrupt Status Register 2

These registers contain status bits for early interrupt for individual analog inputs.

•ADCANCON: ADC Analog Warm-up Control Register

This register contains the warm-up control settings for the analog and bias circuit of the ADC

module.

•ADCDATAx: ADC Output Data Register (‘x’ = 0 through 63)

These registers are the analog-to-digital conversion output data registers. The ADCDATAx

•ADCxCFG: ADCx Configuration Register ‘x’ (‘x’ = 0 through 7)

These registers specify the ADC module configuration data.

•ADCSYSCFG0: ADC System Configuration Register 0 and

ADCSYSCFG1: ADC System Configuration Register 1

These registers contain read-only bits corresponding to the analog input.

ADCTRG6

31:16 — — — TRGSRC23<4:0> —— —

15:0 — — — TRGSRC21<4:0> —— —

ADCTRG7

31:16 — — — TRGSRC27<4:0> —— —

15:0 — — — TRGSRC25<4:0> —— —

ADCTRG8

31:16 — — — TRGSRC31<4:0> —— —

15:0 — — — TRGSRC29<4:0> —— —

ADCCMPCON1

31:16 CVDDATA<15:0>

15:0 — — AINID<5:0> ENDCMP DCMPGIEN DCMPED IEBTWN I

ADCCMPCONx

‘x’ = 2-6

31:16 — — — — — — — — — — — —

15:0 — — — AINID<4:0> ENDCMP DCMPGIEN DCMPED IEBTWN I

ADCFSTAT

31:16 FEN ADC6EN ADC5EN ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN FIEN FRDY FWROVERR —

15:0 FCNT<7:0> FSIGN — — —

ADCFIFO

31:16 DATA<31:16>

15:0 DATA<15:0>

ADCBASE

31:16 — — — — — — — — — — — —

15:0 ADCBASE<15:0>

ADCDMASTAT

31:16 DMAGEN RBFIEN6 RBFIEN5 RBFIEN4 RBFIEN3 RBFIEN2 RBFIEN1 RBFIEN0 DMAWROVERR RBF6 RBF5 RBF4

15:0 DMACNTEN RAFIEN6 RAFIEN5 RAFIEN4 RAFIEN3 RAFIEN2 RAFIEN1 RAFIEN0 — RAF6 RAF5 RAF4

ADCCNTB

31:16 CNTBADDR<31:16>

15:0 CNTBADDR<15:0>

ADCDMAB

31:16 DMABADDR<31:16>

15:0 DMABADDR<15:0>

ADCTRGSNS

31:16 LVL31 LVL30 LVL29 LVL28 LVL27 LVL26 LVL25 LVL24 LVL23 LVL22 LVL21 LVL20

15:0 LVL15 LVL14 LVL13 LVL12 LVL11 LVL10 LVL9 LVL8 LVL7 LVL6 LVL5 LVL4

ADCxTIME

‘x’ = 0-6

31:16 — — — ADCEIS<2:0> SELRES<1:0> DMAEN ADC

15:0 — — — — — — SAMC<9:0>

ADCEIEN1

31:16 EIEN31 EIEN30 EIEN29 EIEN28 EIEN27 EIEN26 EIEN25 EIEN24 EIEN23 EIEN22 EIEN21 EIEN20 E

15:0 EIEN15 EIEN14 EIEN13 EIEN12 EIEN11 EIEN10 EIEN9 EIEN8 EIEN7 EIEN6 EIEN5 EIEN4

ADCEIEN2

31:16 EIEN63 EIEN62 EIEN61 EIEN60 EIEN59 EIEN58 EIEN57 EIEN56 EIEN55 EIEN54 EIEN53 EIEN52 E

15:0 EIEN47 EIEN46 EIEN45 EIEN44 EIEN43 EIEN42 EIEN41 EIEN40 EIEN39 EIEN38 EIEN37 EIEN36 E

ADCEISTAT1

31:16 EIRDY31 EIRDY30 EIRDY29 EIRDY28 EIRDY27 EIRDY26 EIRDY25 EIRDY24 EIRDY23 EIRDY22 EIRDY21 EIRDY20 E

15:0 EIRDY15 EIRDY14 EIRDY13 EIRDY12 EIRDY11 EIRDY10 EIRDY9 EIRDY8 EIRDY7 EIRDY6 EIRDY5 EIRDY4 E

ADCEISTAT2

31:16 EIRDY63 EIRDY62 EIRDY61 EIRDY60 EIRDY59 EIRDY58 EIRDY57 EIRDY56 EIRDY55 EIRDY54 EIRDY53 EIRDY52 E

15:0 EIRDY47 EIRDY46 EIRDY45 EIRDY44 EI DY39 EIRDY38 EIRDY37 EIRDY36 ERDY43 EIRDY42 EIRDY41 EIRDY40 EIR

ADCANCON

31:16 — — — — WKUPCLKCNT<3:0> WKIEN7 WKIEN6 WKIEN5 WKIEN4 W

15:0 WKRDY7 WKRDY6 WKRDY5 WKRDY4 WKRDY3 WKRDY2 WKRDY1 WKRDY0 ANEN7 ANEN6 ANEN5 ANEN4 A

ADCDATAx

('x' = 0 to 63)

31:16 DATA<31:16>

15:0 DATA<15:0>

ADCxCFG

‘x’ = 0-7

(1)

31:16 ADCCFG<31:16>

15:0 ADCCFG<15:0>

ADCSYSCFG0

31:16 AN<31:16>

15:0 AN<15:0>

ADCSYSCFG1

31:16 AN<63:48>

15:0 AN<47:32>

Table 22-1: ADC SFR Summary

Range Bit 31/15 Bit 30/14 Bit 29/13 Bit 28/12 Bit 27/11 Bit 26/10 Bit 25/9 Bit 24/8 Bit 23/7 Bit 22/6 Bit 21/5 Bit 20/4 B

Note 1: Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory-programmed DEVADCx Flash register

registers.

PIC32 Family Reference Manual

bit 10 STRGEN2: ADC2 Presynchronized Triggers bit

1 = ADC2 uses presynchronized triggers

0 = ADC2 does not use presynchronized triggers

bit 9 STRGEN1: ADC1 Presynchronized Triggers bit

1 = ADC1 uses presynchronized triggers

0 = ADC1 does not use presynchronized triggers

bit 8 STRGEN0: ADC0 Presynchronized Triggers bit

1 = ADC0 uses presynchronized triggers

0 = ADC0 does not use presynchronized triggers

bit 7 Unimplemented: Read as ‘ ’

bit 6 SSAMPEN6: ADC6 Synchronous Sampling bit

1 = ADC6 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC6 does not use synchronous sampling

bit 5 SSAMPEN5: ADC5 Synchronous Sampling bit

1 = ADC5 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC5 does not use synchronous sampling

bit 4 SSAMPEN4: ADC4 Synchronous Sampling bit

1 = ADC4 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC4 does not use synchronous sampling

bit 3 SSAMPEN3: ADC3 Synchronous Sampling bit

1 = ADC3 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC3 does not use synchronous sampling

bit 2 SSAMPEN2: ADC2Synchronous Sampling bit

1 = ADC2 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC2 does not use synchronous sampling

bit 1 SSAMPEN1: ADC1 Synchronous Sampling bit

1 = ADC1 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC1 does not use synchronous sampling

bit 0 SSAMPEN0: ADC0 Synchronous Sampling bit

1 = ADC0 uses synchronous sampling for the first sample after being idle or disabled

0 = ADC0 does not use synchronous sampling

Termékspecifikációk

Márka:	Microchip
Kategória:	nincs kategorizálva
Modell:	PIC32MZ1024EFF124

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