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© 2010-2011 Microchip Technology Inc. DS70645C-page 14-1
High-Speed PWM
14
Section 14. High-Speed PWM
HIGHLIGHTS
This section of the manual contains the following major topics:
14.1 Introduction .................................................................................................................. 14-2
14.2 Features....................................................................................................................... 14-2
14.3 Control Registers ......................................................................................................... 14-3
14.4 Architecture Overview................................................................................................ 14-24
14.5 Module Description .................................................................................................... 14-27
14.6 PWM Operating Modes.............................................................................................. 14-33
14.7 PWM Generator......................................................................................................... 14-71
14.8 PWM Trigger.............................................................................................................. 14-87
14.9 PWM Interrupts.......................................................................................................... 14-98
14.10 PWM Fault Pins ......................................................................................................... 14-99
14.11 Special Features ...................................................................................................... 14-105
14.12 PWM Output Pin Control...........................................................................................14-111
14.13 Immediate Update of PWM Duty Cycle ................................................................... 14-113
14.14 Power-Saving Modes............................................................................................... 14-114
14.15 External Control of Individual Time Base(s)............................................................. 14-114
14.16 Application Information ............................................................................................ 14-115
14.17 Register Map............................................................................................................ 14-126
14.18 Related Application Notes........................................................................................ 14-127
14.19 Revision History ....................................................................................................... 14-128
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-2 © 2010-2011 Microchip Technology Inc.
14.1 INTRODUCTION
This section describes the High-Speed Pulse-Width Modulator (PWM) module and its
associated operational modes. The High-Speed PWM module in the dsPIC33E/PIC24E
device family supports a wide variety of PWM modes and is ideal for power
conversion/motor control applications. Some of the common applications include:
• AC-to-DC converters
• DC-to-DC converters
• AC and DC motors: BLDC, PMSM, ACIM, SRM, etc.
• Inverters
• Battery chargers
• Digital lighting
• Uninterrupted Power Supply (UPS)
• Power Factor Correction (PFC) (e.g., Interleaved PFC and Bridgeless PFC)
14.2 FEATURES
The High-Speed PWM module consists of the following major features:
• Up to seven PWM generators, each with an individual time base
• Two PWM outputs per PWM generator
• Individual period and duty cycle for each PWM output
• Duty cycle, dead time, phase shift and frequency resolution equal to the system clock
source (TOSC)
• Independent fault and current-limit inputs for up to 14 PWM outputs
• Redundant Output mode
• Independent Output mode (this feature is not available on all devices)
• Push-Pull Output mode
• Complementary Output mode
• Center-Aligned PWM mode
• Output override control
• Special Event Trigger
• PWM capture feature
• Prescaler for input clock
• ADC triggering with PWM
• Independent PWM frequency, duty cycle and phase shift changes
• Leading-Edge Blanking (LEB) functionality
• Dead time compensation
• Output clock chopping
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33E/PIC24E devices.
Please consult the note at the beginning of the “High-Speed PWM” chapter in the
current device data sheet to check whether this document supports the device you
are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-3
Section 14. High-Speed PWM
High-Speed PWM
14
14.3 CONTROL REGISTERS
The following registers control the operation of the High-Speed PWM module:
•PTCON: PWM Time Base Control Register
- Enables or disables the High-Speed PWM module
- Sets the Special Event Trigger for the ADC
- Enables or disables immediate period updates
- Selects the synchronizing source for the master time base
- Specifies synchronization settings
•PTCON2: PWM Clock Divider Select Register 2
Provides the clock prescaler to the PWM master time base
•PTPER: Primary Master Time Base Period Register
Provides the PWM time period value
•STCON: PWM Secondary Master Time Base Control Registe (1)
- Enables or disables immediate period updates based on the secondary master time base
- Selects the synchronization source for the secondary master time base
- Specifies the synchronization setting for secondary master time base control
• STCON2: PWM Secondary Clock Divider Select Register 2(1)
Provides the clock prescaler to the PWM secondary master time base
•STPER: Secondary Master Time Base Period Register(1)
Provides the secondary master time base period value
•MDC: PWM Master Duty Cycle Register
Provides the PWM master duty cycle value
•SEVTCMP: PWM Special Event Compare Register
Provides the compare value that is used to trigger the ADC module
•SSEVTCMP: PWM Secondary Special Event Compare Register(1)
Provides the compare value that is used to trigger the ADC module based on the
secondary master time base
•CHOP: PWM Chop Clock Generator Register
- Provides the chop clock frequency
- Enables or disables the chop clock generator
•PWMKEY: PWM Unlock Register(1)
Writes the unlock sequence to allow writes to the IOCONx and FCLCONx registers
•PWMCONx: PWM Control Register
- Enables or disables fault interrupt, current-limit interrupt and primary trigger interrupt
- Provides the interrupt status for fault interrupt, current-limit interrupt and primary trigger
interrupt
- Selects the type of time base (master time base or independent time base)
- Selects the type of duty cycle (master duty cycle or independent duty cycle)
- Controls Dead Time mode
- Enables or disables Center-Aligned mode
- Controls the external PWM Reset operation
- Enables or disables immediate updates of the duty cycle, phase offset, independent time
base period
•IOCONx: PWM I/O Control Register
- Enables or disables PWM pin control feature (PWM control or GPIO)
- Controls fault/current limit override values
- Enables PWMxH and PWMxL pin swapping
- Controls the PWMxH and PWMxL output polarity
- Controls the PWMxH and PWMxL output if any of the following modes is selected:
• Complementary mode
• Push-Pull mode
• True Independent mode
Note: Not all registers are available on all devices. Refer to the “High-Speed PWM”
chapter in the specific device data sheet for availability.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-4 © 2010-2011 Microchip Technology Inc.
•FCLCONx: PWM Fault Current-Limit Control Register
- Selects the current-limit control signal source
- Selects the current-limit polarity
- Enables or disables Current-Limit mode
- Selects the fault control signal source
- Configures the fault polarity
- Enables or disables Fault mode
•PDCx: PWM Generator Duty Cycle Register(1)
- Provides the duty cycle value for the PWMxH and PWMxL outputs, if master time base is
selected
- Provides the duty cycle value for the PWMxH output, if independent time base is selected
•PHASEx: PWM Primary Phase Shift Register
- Provides the phase shift value for the PWMxH and PWMxL output, if master time base is
selected
- Provides the independent time base period for the PWMxH output, if independent time
base is selected
•SDCx: PWM Secondary Duty Cycle Register(1,2)
Provides the duty cycle value for the PWMxL output, if independent time base is selected
•SPHASEx: PWM Secondary Phase Shift Register(1,2,3)
- Provides the phase shift for the PWMxL output, if the master time base is selected
- Provides the independent time base period value for the PWMxL output, if the independent
time base is selected
•DTRx: PWM Dead Time Register
- Provides the dead time value for the PWMxH output, if positive dead time is selected
- Provides the dead time value for the PWMxL output, if negative dead time is selected
•ALTDTRx: PWM Alternate Dead Time Register
- Provides the dead time value for the PWMxL output, if positive dead time is selected
- Provides the dead time value for the PWMxH output, if negative dead time is selected
•TRIGx: PWM Primary Trigger Compare Value Register
Provides the compare value to generate the primary PWM trigger
•TRGCONx: PWM Trigger Control Register
- Enables the PWMx trigger postscaler start event
- Specifies the number of PWM cycles to skip before generating the first trigger
•LEBCONx: Leading-Edge Blanking Control Register
- Selects the rising or falling edge of the PWM output for LEB
- Enables or disables LEB for fault and current-limit inputs
•LEBDLYx: Leading-Edge Blanking Delay Register
Provides leading-edge blanking delay for the fault and current-limit inputs
•PWMCAPx: Primary PWM Time Base Capture Register
Provides the captured independent time base value when a leading edge is detected on
the current-limit input, and when LEB processing on the current-limit input signal is
completed
•AUXCONx: PWM Auxiliary Control Register
- Selects PWM state blank and chop clock sources
- Selects PWMxH and PWMxL output chopping functionality
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-5
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-1: PTCON: PWM Time Base Control Register
R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0
PTEN — PTSIDL SESTAT SEIEN EIPU(1) SYNCPOL(1) SYNCOEN(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SYNCEN(1) SYNCSRC<2:0>(1) SEVTPS<3:0>(1)
bit 7 bit 0
Legend: HC = Cleared in Hardware HS = Set in Hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Special Event Interrupt is pending
0 = Special Event Interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Special Event Interrupt is enabled
0 = Special Event Interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit
(1)
1 = SYNCIx/SYNCO polarity is inverted (active-low)
0 = SYNCIx/SYNCO is active-high
bit 8 SYNCOEN: Primary Time Base Sync Enable bit(1)
1 = SYNCO output is enabled
0 = SYNCO output is disabled
bit 7 SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits(1)
These bits select the SYNCIx or PTGOx input as the synchronous source. Refer to the “High-Speed
PWM” chapter in the specific device data sheet for availability.
bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits
(1)
1111 = 1:16 postscaler generates Special Event trigger at every 16th compare match event
•
•
•
0001 = 1:2 postscaler generates Special Event trigger at every second compare match event
0000 = 1:1 postscaler generates Special Event trigger at every compare match event
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-6 © 2010-2011 Microchip Technology Inc.
Register 14-2: PTCON2: PWM Clock Divider Select Register 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PCLKDIV<2:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide by 64
101 = Divide by 32
100 = Divide by 16
011 = Divide by 8
010 = Divide by 4
001 = Divide by 2
000 = Divide by 1, maximum PWM timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
Register 14-3: PTPER: Primary Master Time Base Period Register
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PTPER<15:8>(1)
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
PTPER<7:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits(1)
Note 1: 1 LSb = 1 Tosc. For example, 7.14 ns for 70 MIPS operation.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-7
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-4: STCON: PWM Secondary Master Time Base Control Registe (1)
U-0 U-0 U-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — SESTAT SEIEN EIPU(2) SYNCPOL SYNCOEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SYNCEN SYNCSRC<2:0> SEVTPS<3:0>
bit 7 bit 0
Legend: HC = Cleared in Hardware HS = Set in Hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Secondary Special Event Interrupt is pending
0 = Secondary Special Event Interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Secondary Special Event Interrupt is enabled
0 = Secondary Special Event Interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(2)
1 = Active Secondary Period register is updated immediately
0 = Active Secondary Period register updates occur on PWM cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit
1 = SYNCO2 output is active-low
0 = SYNCO2 output is active-high
bit 8 SYNCOEN: Secondary Master Time Base Sync Enable bit
1 = SYNCO2 output is enabled
0 = SYNCO2 output is disabled
bit 7 SYNCEN: External Secondary Master Time Base Synchronization Enable bit
1 = External synchronization of secondary time base is enabled
0 = External synchronization of secondary time base is disabled
bit 6-4 SYNCSRC<2:0>: Secondary Time Base Sync Source Selection bits
These bits select the SYNCIx or PTGOx input as the synchronous source. Refer to the “High-Speed
PWM” chapter in the specific device data sheet for availability.
bit 3-0 SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits
1111 = 1:16 Postscale
•
•
•
0001 = 1:2 Postscale
0000 = 1:1 Postscale
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
2: This bit only applies to the secondary master time base period.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-8 © 2010-2011 Microchip Technology Inc.
Register 14-5: STCON2: PWM Secondary Clock Divider Select Register 2
(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PCLKDIV<2:0>(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(2)
111 = Reserved
110 = Divide by 64
101 = Divide by 32
100 = Divide by 16
011 = Divide by 8
010 = Divide by 4
001 = Divide by 2
000 = Divide by 1, maximum PWM timing resolution (power-on default)
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-9
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-6: STPER: Secondary Master Time Base Period Register
(1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
STPER<15:8>
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
STPER<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 STPER<15:0>: Secondary Master Time Base Period Value bits
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
Register 14-7: MDC: PWM Master Duty Cycle Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 MDC<15:0>: Master PWM Duty Cycle Value bits
Register 14-8: SEVTCMP: PWM Special Event Compare Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SEVTCMP<15:0>: Special Event Compare Count Value bits
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-10 © 2010-2011 Microchip Technology Inc.
Register 14-9: SSEVTCMP: PWM Secondary Special Event Compare Register
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEVTCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEVTCMP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SSEVTCMP<15:0>: Secondary Special Event Compare Count Value bits
The optional SSEVTCMP register and the optional secondary master time base provide an additional
Special Event Trigger. The secondary special event trigger also has its own postscaler controlled by
the SEVTPS<3:0> bits in the STCON register.
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
Register 14-10: CHOP: PWM Chop Clock Generator Register
R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
CHPCLKEN — — — — — CHOPCLK<9:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHOPCLK<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CHPCLKEN: Enable Chop Clock Generator bit
1 = Chop clock generator is enabled
0 = Chop clock generator is disabled
bit 14-10 Unimplemented: Read as ‘0’
bit 9-0 CHOPCLK<9:0>: Chop Clock Divider bits
Chop Frequency = (FP/PLKDIV) / (CHOPCLK<9:0> + 1)
As an example, for devices running at 60 MIPS, a value of all zeros will yield a 60 MHz chop clock
(period = 16.7 ns) with the PWM clock prescaler configured for fastest clock. A value of ‘0000000001’
in the CHOPCLK<9:0> bits will yield a 30 MHz chop clock with the PWM clock prescaler configured
for fastest clock.
Note: The chop clock generator operates with the Primary PWM Clock Prescaler bits (PCLKDIV<2:0>) in the
PTCON2 register.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-11
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-11: PWMKEY: PWM Unlock Register(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWMKEY<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWMKEY<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PWMKEY<15:0>: PWM Unlock bits
If the PWMLOCK Configuration bit is asserted (PWMLOCK = 1), the IOCONx and FCLCONx registers
are writable only after the proper sequence is written to the PWMKEY register. If the PWMLOCK
Configuration bit is deasserted (PWMLOCK = 0), the IOCONx and FCLCONx registers are writable at
all times. Refer to 14.5.3 “Write Protection” for further details of the unlock sequence.
Note 1: This register is implemented only in devices where the PWMLOCK Configuration bit is present in the
FOSCSEL Configuration register.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-13
Section 14. High-Speed PWM
High-Speed PWM
14
bit 7-6 DTC<1:0>: Dead Time Control bits
11 = Dead Time Compensation mode enabled
10 = Dead time function is disabled
01 = Negative dead time actively applied for Complementary Output mode(6)
00 = Positive dead time actively applied for all output modes
bit 5 DTCP: Dead Time Compensation Polarity bit(5)
1 = If DTCMPx pin = 0, PWMxL is shortened, and PWMxH is lengthened
If DTCMPx pin = 1, PWMxH is shortened, and PWMxL is lengthened
0 = If DTCMPx pin = 0, PWMxH is shortened, and PWMxL is lengthened
If DTCMPx pin = 1, PWMxL is shortened, and PWMxH is lengthened
bit 4 Unimplemented: Read as ‘0’
bit 3 MTBS: Master Time Base Select bit
1 = PWM generator uses the secondary master time base for synchronization and the clock source
for the PWM generation logic (if secondary time base is available)
0 = PWM generator uses the primary master time base for synchronization and the clock source for
the PWM generation logic
bit 2 CAM: Center-Aligned Mode Enable bit(2,3)
1 = Center-Aligned mode is enabled
0 = Edge-Aligned mode is enabled
bit 1 External PWM Reset Control bitXPRES: (4)
1 = Current-limit source resets primary local time base for this PWM generator if it is in Independent
Time Base mode
0 = External pins do not affect PWM time base
bit 0 IUE: Immediate Update Enable bit(3)
1 = Updates to the active MDC/PDCx/SDCx/DTRx/ALTDTRx/PHASEx/SPHASEx registers are
immediate
0 = Updates to the active MDC/PDCx/SDCx/DTRx/ALTDTRx/PHASEx/SPHASEx registers are
synchronized to the PWM time base
Register 14-12: PWMCONx: PWM Control Register (Continued)
Note 1: Software must clear the interrupt status here, and in the corresponding IFS bit in the Interrupt Controller.
2: The Independent Time Base mode (ITB = 1 0) must be enabled to use Center-Aligned mode. If ITB = , the
CAM bit is ignored.
3: These bits should not be changed after the PWM is enabled (PTEN = 1).
4: To operate in External Period Reset mode, the ITB bit must be set to ‘ ’ and the CLMOD bit in the 1
FCLCONx register must be set to ‘0’.
5: For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored.
6: Negative dead time is only implemented for Edge-Aligned mode (CAM = 0).
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-14 © 2010-2011 Microchip Technology Inc.
Register 14-13: IOCONx: PWM I/O Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OVRDAT<1:0> FLTDAT<1:0>(1,2) CLDAT<1:0> SWAP OSYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PENH: PWMxH Output Pin Ownership bit
1 = PWM module controls PWMxH pin
0 = GPIO module controls PWMxH pin
bit 14 PENL: PWMxL Output Pin Ownership bit
1 = PWM module controls PWMxL pin
0 = GPIO module controls PWMxL pin
bit 13 POLH: PWMxH Output Pin Polarity bit
1 = PWMxH pin is active-low
0 = PWMxH pin is active-high
bit 12 POLL: PWMxL Output Pin Polarity bit
1 = PWMxL pin is active-low
0 = PWMxL pin is active-high
bit 11-10 PMOD<1:0>: PWM # I/O Pin Mode bits
11 = PWM I/O pin pair is in True Independent PWM Output mode
(3)
10 = PWM I/O pin pair is in Push-Pull Output mode
01 = PWM I/O pin pair is in Redundant Output mode
00 = PWM I/O pin pair is in Complementary Output mode
bit 9 OVRENH: Override Enable for PWMxH Pin bit
1 = OVRDAT<1> provides data for output on PWMxH pin
0 = PWM generator provides data for PWMxH pin
bit 8 OVRENL: Override Enable for PWMxL Pin bit
1 = OVRDAT<0> provides data for output on PWMxL pin
0 = PWM generator provides data for PWMxL pin
bit 7-6 OVRDAT<1:0>: State(2) for PWMxH, PWMxL Pins if Override is Enabled bits
If OVERENH = 1, OVRDAT<1> provides data for PWMxH
If OVERENL = 1, OVRDAT<0> provides data for PWMxL
Note 1: These bits must not be changed after the PWM module is enabled (PTEN = 1).
2: State represents Active/Inactive state of the PWM, depending on the POLH and POLL bits. For example, if
FLTDAT<1> is set to ‘1’ and POLH is set to ‘1’, the PWMxH pin will be at logic level 0 (active level) when a
fault occurs.
3: This feature is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific device
data sheet for availability.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-15
Section 14. High-Speed PWM
High-Speed PWM
14
bit 5-4 FLTDAT<1:0>: State(2) for PWMxH and PWMxL Pins if FLTMOD is Enabled bits(1)
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If fault is active, FLTDAT<1> provides the state for PWMxH.
If fault is active, FLTDAT<0> provides the state for PWMxL.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:
If current-limit is active, FLTDAT<1> provides the state for PWMxH.
If fault is active, FLTDAT<0> provides the state for PWMxL.
bit 3-2 CLDAT<1:0>: State(2) for PWMxH and PWMxL Pins if CLMOD is Enabled bits
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If current-limit is active, CLDAT<1> provides the state for PWMxH.
If current-limit is active, CLDAT<0> provides the state for PWMxL.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:
The CLDAT<1:0> bits are ignored.
bit 1 SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to PWMxL pin; PWMxL output signal is connected to PWMxH
pin
0 = PWMxH and PWMxL output signals pins are mapped to their respective pins
bit 0 OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base
0 = Output overrides via the OVRDAT<1:0> bits occur on next CPU clock boundary
Register 14-13: IOCONx: PWM I/O Control Register (Continued)
Note 1: These bits must not be changed after the PWM module is enabled (PTEN = 1).
2: State represents Active/Inactive state of the PWM, depending on the POLH and POLL bits. For example, if
FLTDAT<1> is set to ‘1’ and POLH is set to ‘1’, the PWMxH pin will be at logic level 0 (active level) when a
fault occurs.
3: This feature is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific device
data sheet for availability.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-16 © 2010-2011 Microchip Technology Inc.
Register 14-14: FCLCONx: PWM Fault Current-Limit Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFLTMOD(4) CLSRC<4:0>(2,3) CLPOL(1) CLMOD
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTSRC<4:0>(2,3) FLTPOL(1) FLTMOD<1:0>(4)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IFLTMOD: Independent Fault Mode Enable bit
(4)
1 = Independent Fault mode: Current-limit input maps FLTDAT<1> to PWMxH output, and fault input
maps FLTDAT<0> to PWMxL output. The CLDAT<1:0> bits are not used for override functions.
0= Normal Fault mode: Current-limit and fault inputs map CLDAT<1:0> and FLTDAT<1:0> to PWMxH
and PWMxL outputs.
bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select bits for PWM Generator #
(2,3)
These bits specify the current-limit control signal source. Refer to the “High-Speed PWM” chapter of
the specific device data sheet for available selections.
bit 9 CLPOL: Current-Limit Polarity bit for PWM Generator #(1)
1 = The selected current-limit source is active-low
0 = The selected current-limit source is active-high
bit 8 CLMOD: Current-Limit Mode Enable bit for PWM Generator #
1 = Current-Limit mode is enabled
0 = Current-Limit mode is disabled
bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select bits for PWM Generator #
(2,3)
These bits specify the Fault control source. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for available selections.
bit 2 FLTPOL: Fault Polarity bit for PWM Generator #(1)
1 = The selected fault source is active-low
0 = The selected fault source is active-high
bit 1-0 FLTMOD<1:0>: Fault Mode bits for PWM Generator #(4)
11 = Fault input is disabled
10 = Reserved
01 = The selected fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle)
00 = The selected fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition)
Note 1: These bits should be changed only when PTEN = 0. Changing the polarity selection during operation will
yield unpredictable results.
2: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode
(FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an
unused current-limit source to prevent the current-limit source from disabling both the PWMxH and
PWMxL outputs.
3: When Independent Fault mode is enabled (IFLTMOD = 1), and Fault 1 is used for Current-Limit mode
(CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused
fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs.
4: This feature is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific device
data sheet for availability.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-18 © 2010-2011 Microchip Technology Inc.
Register 14-17: SDCx: PWM Secondary Duty Cycle Register(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SDCx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SDCx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SDCx<15:0>: Secondary Duty Cycle bits for PWMxL output pin
Note 1: The SDCx register is used in Independent PWM mode only (PMOD<1:0> (IOCONx<11:10>) = 11. When
used in Independent PWM mode, the SDCx register controls the PWMxL duty cycle.
2: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
Register 14-18: SPHASEx: PWM Secondary Phase Shift Register
(1,2,3)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPHASEx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPHASEx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SPHASEx<15:0>: Secondary Phase Offset bits for PWMxL Output Pin
Note 1: If the ITB bit = 0 (PWMCONx<9>), the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00,
01 10, or ) SPHASEx<15:0> = Not used
• True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11) SPHASEx<15:0> = Phase
shift value for PWMxL only
2: If the ITB bit = 1 (PWMCONx<9>), the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00,
01 10, or ) SPHASEx<15:0> = Not used
• True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11) SPHASEx<15:0> =
Independent time base period value for PWMxL only
3: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific device
data sheet for availability.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-19
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-19: DTRx: PWM Dead Time Register
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DTRx<13:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DTRx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-0 DTRx<13:0>: Unsigned 14-bit Dead Time Value bits for PWMx Dead Time Unit
Register 14-20: ALTDTRx: PWM Alternate Dead Time Register
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — ALTDTRx<13:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ALTDTRx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-0 ALTDTRx<13:0>: Unsigned 14-bit Dead Time Value bits for PWMx Dead Time Unit
Register 14-21: TRIGx: PWM Primary Trigger Compare Value Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRGCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRGCMP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TRGCMP<15:0>: Trigger Control Value bits
When the primary PWM functions in local time base, this register contains the compare values that
can trigger the ADC module.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-20 © 2010-2011 Microchip Technology Inc.
Register 14-22: TRGCONx: PWM Trigger Control Register
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
TRGDIV<3:0> — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — TRGSTRT<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits
1111 = Trigger output for every 16th trigger event
•
•
•
0010 = Trigger output for every 3rd trigger event
0001 = Trigger output for every 2nd trigger event
0000 = Trigger output for every trigger event
bit 11-6 Unimplemented: Read as ‘0’
bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits
111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled
•
•
•
000010 = Wait 2 PWM cycles before generating the first trigger event after the module is enabled
000001 = Wait 1 PWM cycles before generating the first trigger event after the module is enabled
000000 = Wait 0 PWM cycles before generating the first trigger event after the module is enabled
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-21
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-23: LEBCONx: Leading-Edge Blanking Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
PHR PHF PLR PLF FLTLEBEN CLLEBEN — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — BCH(1) BCL(1) BPHH BPHL BPLH BPLL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PHR: PWMxH Rising Edge Trigger Enable bit
1 = Rising edge of PWMxH will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores rising edge of PWMxH
bit 14 PHF: PWMxH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores falling edge of PWMxH
bit 13 PLR: PWMxL Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores rising edge of PWMxL
bit 12 PLF: PWMxL Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores falling edge of PWMxL
bit 11 FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected fault input
0 = Leading-Edge Blanking is not applied to selected fault input
bit 10 CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected current-limit input
0 = Leading-Edge Blanking is not applied to selected current-limit input
bit 9-6 Unimplemented: Read as ‘0’
bit 5 BCH: Blanking in Selected Blanking Signal High Enable bit(1)
1 = State blanking (of current-limit and/or fault input signals) when selected blanking signal is high
0 = No blanking when selected blanking signal is high
bit 4 BCL: Blanking in Selected Blanking Signal Low Enable bit
(1)
1 = State blanking (of current-limit and/or fault input signals) when selected blanking signal is low
0 = No blanking when selected blanking signal is low
bit 3 BPHH: Blanking in PWMxH High Enable bit
1 = State blanking (of current-limit and/or fault input signals) when PWMxH output is high
0 = No blanking when PWMxH output is high
bit 2 BPHL: Blanking in PWMxH Low Enable bit
1 = State blanking (of current-limit and/or fault input signals) when PWMxH output is low
0 = No blanking when PWMxH output is low
bit 1 BPLH: Blanking in PWMxL High Enable bit
1 = State blanking (of current-limit and/or fault input signals) when PWMxL output is high
0 = No blanking when PWMxL output is high
bit 0 BPLL: Blanking in PWMxL Low Enable bit
1 = State blanking (of current-limit and/or fault input signals) when PWMxL output is low
0 = No blanking when PWMxL output is low
Note 1: The blanking signal is selected via the BLANKSEL<3:0> bits (AUXCONx<11:8>).
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-22 © 2010-2011 Microchip Technology Inc.
Register 14-24: LEBDLYx: Leading-Edge Blanking Delay Register
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — LEB<11:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEB<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-0 LEB<11:0>: Leading-Edge Blanking Delay bits for Current-Limit and Fault Inputs
Register 14-25: PWMCAPx: Primary PWM Time Base Capture Register
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
PWMCAP<15:8>(1,2)
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
PWMCAP<7:0>(1,2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PWMCAP<15:0>: Captured PWM Time Base Value bits(1,2)
The value in this register represents the captured PWM time base value when a leading edge is
detected on the current-limit input.
Note 1: The capture feature is only available on the primary output (PWMxH).
2: The feature is only active after LEB processing on the current-limit input signal is complete.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-23
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-26: AUXCONx: PWM Auxiliary Control Register
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — BLANKSEL<3:0>(1)
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CHOPSEL<3:0>(1) CHOPHEN CHOPLEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 BLANKSEL<3:0>: PWM State Blank Source Select bits(1)
The selected state blank signal blocks the current-limit and/or fault input signals (if enabled via the
BCH and BCL bits in the LEBCONx register).
1111 = PWMxH selected as state blank source
•
•
•
0001 = PWMxH selected as state blank source
0000 = No state blanking
bit 7-6 Unimplemented: Read as ‘0’
bit 5-2 CHOPSEL<3:0>: PWM Chop Clock Source Select bits(1)
The selected signal will enable and disable (CHOP) the selected PWM outputs.
1111 = PWMxH selected as CHOP clock source
•
•
•
0001 = PWMxH selected as CHOP clock source
0000 = Chop clock generator selected as CHOP clock source
bit 1 CHOPHEN: PWMxH Output Chopping Enable bit
1 = PWMxH chopping function is enabled
0 = PWMxH chopping function is disabled
bit 0 CHOPLEN: PWMxL Output Chopping Enable bit
1 = PWMxL chopping function is enabled
0 = PWMxL chopping function is disabled
Note 1: These bit selections are device dependent. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-24 © 2010-2011 Microchip Technology Inc.
14.4 ARCHITECTURE OVERVIEW
Figure 14-1 illustrates the architectural overview of the High-Speed PWM module and its
interconnection with the CPU and other peripherals.
Figure 14-1: High-Speed PWM Module Architectural Overview(1)
CPU
Primary and Secondary
PWM
Generator 1
PWM
Generator 2
PWM
Generator x
PWM
Generator x
SYNCIx
SYNCOx
PWM1H
PWM1L
PWM1 Interrupt
PWM2H
PWM2L
PWM2 Interrupt
PWMxH
PWMxL
PWMx Interrupt
PWMxH
PWMxL
PWMx Interrupt
Synchronization Signal
Data Bus
ADC Module
FLTx and
Synchronization Signal
Synchronization Signal
Synchronization Signal
Primary Trigger
Primary Special
DTCMPx
Secondary Special
Event Trigger
Event Trigger Fault, Current-Limit
and Dead-Time Compensation
Master Time Base
Fault, Current-Limit
and Dead-Time Compensation
Fault, Current-Limit
and Dead-Time Compensation
Fault, Current-Limit
and Dead-Time Compensation
Note 1: Not all of the features and registers listed in this block diagram are available on all devices. Refer to the
“High-Speed PWM” chapter of the specific device data sheet for availability.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-25
Section 14. High-Speed PWM
High-Speed PWM
14
The High-Speed PWM module contains multiple PWM generators. Each PWM generator
provides two PWM outputs: PWMxH and PWMxL. A master time base generator provides a
synchronous signal as a common time base to synchronize the various PWM outputs. Each
generator can operate independently or in sync with the master time base.
The individual PWM
outputs are available on the output pins of the device. The input fault signals and current-limit
signals, when enabled, monitor and protect the system by placing the PWM outputs into a known
“safe” state.
Each PWM generator can create a trigger to the ADC module to sample the analog signal at a
specific instance during the PWM period. In addition, the High-Speed PWM module also
generates a Special Event Trigger to the ADC module based on the master time base.
The High-Speed PWM module can synchronize itself with an external signal or can act as a
synchronizing source to any external device. The SYNCIx is the input pin, which can synchronize
the High-Speed PWM module with an external signal. The SYNCOx pin is an output pin that
provides a synchronous signal to an external device.
The High-Speed PWM module can be used for a wide variety of power conversion/motor control
applications that require:
• High operating frequencies with good resolution
• Ability to dynamically control PWM parameters such as duty cycle, period and dead time
• Ability to independently control each PWM
• Ability to synchronously control all PWMs
• Independent resource allocation for each PWM generator
• Fault handling capability
• CPU load staggering to execute multiple control loops
Each function of the High-Speed PWM module is described in detail in subsequent sections.
Figure 14-2 illustrates the interconnections between various registers in the High-Speed PWM
module.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-26 © 2010-2011 Microchip Technology Inc.
Figure 14-2: High-Speed PWM Module Register Interconnection Diagram
MUX
PTMRx
PDCx
PWMCONx TRGCONx
PTCON, PTCON2
IOCONx
DTRx
PWMxL
PWMxH
FLTx
PWM1L
PWM1H
FCLCONx
MDC
PHASEx
LEBCONx
MUX
STMRx
SDCx
SPHASEx ALTDTRx
PWMCAPx
User Override Logic
Current-Limit
PWM Output Mode
Control Logic
Dead
Logic
Pin
Control
Logic
Fault and
Current-Limit
Logic
PWM Generator 1
FLTx
PWM Generator x
Interrupt
Logic
ADC Trigger
Module Control and Timing
Master Duty Cycle Register
Synchronization Synchronization
Master PeriodMaster Period
Master Duty CycleMaster Duty Cycle
Secondary PWM
SYNCI2
SYNCI1
SYNCO1
SEVTCMP
Comparator Special Event Trigger
Special Event
Postscaler
PTPER
PMTMR Primary Master Time Base
Master Time Base Counter
Special Event Compare Trigger
Comparator
Clock
Prescaler
Comparator
Comparator
Comparator
16-bit Data Bus
Time
TRIGx Fault Override Logic
Override Logic
SYNCO2
SEVTCMP
Comparator Special Event Trigger
Special Event
Postscaler
PTPER
PMTMR Secondary Master Time Base
Master Time Base Counter
Special Event Compare Trigger
Comparator
Clock
Prescaler
DTCMPx
DTCMP1
Note 1: Not all of the features and registers listed in this block diagram are available on all devices. Refer to the
“High-Speed PWM” chapter of the specific device data sheet for availability.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-28 © 2010-2011 Microchip Technology Inc.
14.5.4 Standard Edge-Aligned PWM
The standard edge-aligned PWM waveforms are illustrated in Figure 14-3. To create the
edge-aligned PWM, a timer or counter circuit counts upward from zero to a specified maximum
value, called Period. Another register contains the duty cycle value, which is constantly
compared with the timer value. When the timer or counter value is less than or equal to the duty
cycle value, the PWM output signal is asserted. When the timer value exceeds the duty cycle
value, the PWM signal is deasserted. When the timer value is greater than or equal to the period
value, the timer resets itself and the process repeats.
Figure 14-3: Standard Edge-Aligned PWM Mode
14.5.5 Center-Aligned PWM
The center-aligned PWM waveforms illustrated in Figure 14-4, align the PWM signals with
respect to a reference point so that half of the PWM signal occurs before the reference point and
the remaining half of the signal occurs after the reference point. The Center-Aligned mode is
enabled when the CAM bit (PWMCONx<2>) is set.
When operating in Center-Aligned mode, the effective PWM period is twice the value specified
in the PHASEx registers, because the independent time base counter in the PWM generator is
counting up and then counting down during the cycle. The up/down count sequence doubles the
effective PWM cycle period. This mode is used in many motor control applications.
Note: The Independent Time Base mode (ITB = 1) must be enabled to use the
Center-Aligned mode. If ITB = 0, the CAM bit is ignored.
PDC1
Period
Value
Timer
Value
Duty Cycle Match Timer Resets
Period
Duty Cycle
0
Period
TOFFTON
PWMxH
PWMxH
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-29
Section 14. High-Speed PWM
High-Speed PWM
14
Figure 14-4: Center-Aligned PWM Mode
Example 14-2: Edge-Aligned or Center-Aligned Mode Selection
PWM1H
PWM2H
0
PDC1
PDC2
PHASEx
Period
2 x Period
/* Select Edge-Aligned PWM Time Base */
PWMCON1bits.CAM = 0; /* For Edge-Aligned mode */
/* Select Center-Aligned PWM Time Base */
PWMCON1bits.CAM = 1; /* For Center-Aligned mode */
PWMCON1bits.ITB = 1; /* Must be set for Center-Aligned mode */
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-30 © 2010-2011 Microchip Technology Inc.
14.5.6 Master Time Base/Synchronous Time Base
Figure 14-5 illustrates the PWM functionality in the master time base.
Figure 14-5: Master Time Base Block Diagram
Some of the common tasks of the master time base are as follows:
• Generates time reference for all the PWM generators
• Generates special event ADC trigger and interrupt
• Supports synchronization with the external SYNC signal (SYNCIx)
• Supports synchronization with external devices using SYNCOx signal
The master time base for a PWM generator is set by loading a 16-bit value into the Primary
Master Time Base Period register (PTPER). In Master Time Base mode, the value in the
PHASEx and SPHASEx registers provides phase shift between the PWM outputs.
The clock for
the PWM timer (PMTMR) is derived from the system clock.
14.5.7 Time Base Synchronization
The master time base can be synchronized with the external synchronization signal via the
master time base synchronization signal (SYNCIx). The synchronization source (SYNCIx) can
be selected using the SYNCSRC<1:0> bits (PTCON<5:4>). The SYNCPOL bit (PTCON<9>)
selects the rising or falling edge of the synchronization pulse, which resets the timer (PMTMR).
The external synchronization feature can be enabled or disabled with the SYNCEN bit
(PTCON<7>). The pulse-width of the external synchronization signal (SYNCIx) must be more
than the period of the post-scaled input clock to ensure reliable detection by the master time
base.
M
U
X
SYNCSRC
PMTMR
SEVTCMP
1:1
1:16
PTPER
SEVTPS
Reset
SYNCEN
SYNCI1
SYNCI2
SYNCOEN
SYNCO
Edge Detector
SYNCPOL
Special Event
Trigger to ADC
Synchronization Signal
PWM Clock
CMP
CMP
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-31
Section 14. High-Speed PWM
High-Speed PWM
14
An external device can also be synchronized with the master time base using the
Synchronization Output (SYNCOx) signal. The SYNCOx signal is generated when the PTPER
register resets the PMTMR register. The SYNCOx signal pulse is 12 * TCY to ensure other
devices reliably sense the signals. The polarity of the SYNCOx signal is determined by the
SYNCPOL bit (PTCON<9>). The SYNCOx signal can be enabled or disabled by selecting the
SYNCOEN bit (PTCON<8>).
The advantage of synchronization is that it ensures the beat frequencies are not generated when
multiple power controllers are in use.
Example 14-3: Synchronizing Master Time Base with External Signal
Example 14-4: Synchronizing External Device with Master Time Base
14.5.8 Special Event Trigger
The High-Speed PWM module has a master Special Event Trigger that can be used for
synchronization of analog-to-digital conversions with the PWM time base. The analog-to-digital
sampling and conversion time can be programmed to occur within the PWM period. The Special
Event Trigger allows the user-assigned application to minimize the delay between the time the
conversion results are acquired and the time the duty cycle value is updated. The Special Event
Trigger is based on the master time base.
The master Special Event Trigger value is loaded into the PWM Special Event Compare register
(SEVTCMP). In addition, the SEVTPS<3:0> bits (PTCON<3:0>), control the Special Event
Trigger operation. To generate a trigger to the ADC module, the value in the PTPER register is
compared with the value in the SEVTCMP register. The master Special Event Trigger has a
postscaler that allows a 1:1 to 1:16 postscaler ratio. The postscaler is configured by writing to the
SEVTPS<3:0> bits (PTCON<3:0>).
The Special Event Trigger pulses are always generated during the following instances:
• On a match condition regardless of the status of the Special Event Interrupt Enable bit
(SEIEN)
• If the compare value in the SEVTCMP register is a value from zero to a maximum value of
the PTPER register
Note 1: The SYNCIx pulse should be greater than the PWM period value.
2: The SYNCIx pulse should be continuous with a minimum pulse-width of 200 ns.
3: The PWM cycles are expected to be distorted for the first two SYNCIx pulses.
4: The period value should be a multiple of 8 (Least Significant 3 bits set to ‘0’) for the
external synchronization to work in the Push-Pull mode.
5: There is a delay from the input of a SYNC signal until the internal time base counter
is Reset. This will be approximately 2.5 * prescale clock period.
6: The External Time Base Synchronization must not be used with phase shifted PWM
as the synchronization signal may not maintain the phase relationships between the
multiple PWM channels.
7: The External Time Base Synchronization cannot be used in Independent Time
Base mode.
/* Synchronizing Master Time Base with External Signal */
PTCONbits.SYNCSRC = 0; /* Select SYNC1 input as synchronizing source */
PTCONbits.SYNCPOL = 0; /* Rising edge of SYNC1 resets the PWM Timer */
PTCONbits.SYNCEN = 1; /* Enable external synchronization */
/* Synchronizing External Device with Master Time Base */
PTCONbits.SYNCPOL = 0; /* SYNCO output is active-high */
PTCONbits.SYNCOEN = 1; /* Enable SYNCO output */
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-33
Section 14. High-Speed PWM
High-Speed PWM
14
14.6 PWM OPERATING MODES
The High-Speed PWM module supports the following operation modes:
• Push-Pull Output mode
• Complementary Output mode
• Redundant Output mode
• Independent Output mode (this feature is not available on all devices)
These operating modes can be selected using the PMOD<1:0> bits (IOCONx<11:10>).
In the following sections, figures and examples are provided, which show the PWM outputs in
multiple operating modes. Table 14-1 provides a list of the available modes and settings, with
references to the figures by number.
Table 14-1: Mode and Code Cross-reference Table
PWM Mode Mode Settings Related
Figure
Push-Pull Independent Duty Cycle and Phase, Fixed Primary Period, Edge-Aligned 14-7
Independent Duty Cycle and Phase, Fixed Secondary Period, Edge-Aligned 14-8
Master Duty Cycle and Independent Phase, Fixed Primary Period, Edge-Aligned 14-9
Master Duty Cycle and Independent Phase, Fixed Secondary Period, Edge-Aligned 14-10
Independent Duty Cycles and Periods, No Phase-Shifting, Edge-Aligned 14-11
Master Duty Cycles and Independent Periods, No Phase-Shifting, Edge-Aligned 14-12
Independent Duty Cycles and Periods, No Phase-Shifting, Center-Aligned Mode 14-13
Master Duty Cycles and Independent Periods, No Phase-Shifting, Center-Aligned Mode 14-14
Complementary Independent Duty Cycle and Phase, Fixed Primary Period, Edge-Aligned 14-15
Independent Duty Cycle and Phase, Fixed Secondary Period, Edge-Aligned 14-16
Master Duty Cycle and Independent Phase, Fixed Primary Period, Edge-Aligned 14-17
Master Duty Cycle and Independent Phase, Fixed Secondary Period, Edge-Aligned 14-18
Independent Duty Cycles and Periods, No Phase-Shifting, Edge-Aligned 14-19
Master Duty Cycles and Independent Periods, No Phase-Shifting, Edge-Aligned 14-20
Independent Duty Cycles and Periods, No Phase-Shifting, Center-Aligned 14-21
Master Duty Cycles and Independent Periods, No Phase-Shifting, Center-Aligned 14-22
Redundant Independent Duty Cycle and Phase, Fixed Primary Period, Edge-Aligned 14-23
Independent Duty Cycle and Phase, Fixed Secondary Period, Edge-Aligned 14-24
Master Duty Cycle and Variable Phase, Fixed Primary Period, Edge-Aligned 14-25
Master Duty Cycle and Variable Phase, Fixed Secondary Period, Edge-Aligned 14-26
Independent Duty Cycles and Periods, No Phase-Shifting, Edge-Aligned 14-27
Master Duty Cycles and Independent Periods, No Phase-Shifting, Edge-Aligned 14-28
Independent Duty Cycles and Periods, No Phase-Shifting, Center-Aligned 14-29
Master Duty Cycles and Independent Periods, No Phase-Shifting, Center-Aligned 14-30
Independent Independent Duty Cycle and Phase, Fixed Primary Period, Edge-Aligned 14-31
Independent Duty Cycle and Phase, Fixed Secondary Period, Edge-Aligned 14-32
Master Duty Cycle, Variable Phase, Fixed Primary Period, Edge-Aligned 14-33
Master Duty Cycle, Variable Phase, Fixed Secondary Period, Edge-Aligned 14-34
Independent Duty Cycles and Periods, No Phase-Shifting, Edge-Aligned 14-35
Master Duty Cycles, Independent Periods, No Phase-Shifting, Edge-Aligned 14-36
Independent Duty Cycles and Periods, No Phase-Shifting, Center-Aligned 14-37
Master Duty Cycles, Independent Periods, No Phase-Shifting, Center-Aligned 14-38
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-34 © 2010-2011 Microchip Technology Inc.
14.6.1 Push-Pull PWM Mode
In Push-Pull mode, the PWM outputs are alternately available on the PWMxH and PWMxL pins.
Some typical applications of Push-Pull mode are provided in 14.16 “Application Information”.
Figure 14-7 through Figure 14-14 and Example 14-6 through Example 14-13 show the PWM
outputs for Push-Pull PWM mode in multiple operating modes.
Figure 14-7: Push-Pull PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Note: Not all of the features and registers listed in the Figures and Code Examples in this
section are available on all devices. Refer to the “High-Speed PWM” chapter of the
specific device data sheet for availability.
PTPER
PHASE1 = 0
PHASE2
PHASE3
PDC1
Where:
PHASEx Phase of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
PTPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
PDC1
PDC2
PDC2
PDC3
PDC3
Complete
PWM1L Cycle
DTR1
ALTDTR1
ALTDTR2
DTR2
ALTDTR3
DTR3
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-35
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-6: Push-Pull PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-8: Push-Pull PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base */
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
PDC1 = 150;
PDC2 = 200;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Primary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0000;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
Where:
PHASEx Phase of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
STPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
STPER
PHASE1 = 0
PHASE2
PHASE3
PDC1
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
PDC1
PDC2
PDC2
PDC3
PDC3
Complete
PWM1L Cycle
DTR1
ALTDTR1
ALTDTR2
DTR2
ALTDTR3
DTR3
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-36 © 2010-2011 Microchip Technology Inc.
Example 14-7: Push-Pull PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
Figure 14-9: Push-Pull PWM Mode – Master Duty Cycle and Independent Phase, Fixed Primary Period,
Edge-Aligned
/* Set PWM Period on Secondary Time Base */
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
PDC1 = 150;
PDC2 = 200;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Secondary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0008;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
Where:
PHASEx Phase of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
PTPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
PTPER
PHASE1 = 0
PHASE2
PHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
MDC
MDC
MDC
MDC
MDC
Complete
PWM1L Cycle
DTR1
ALTDTR1
ALTDTR2
DTR2
ALTDTR3
DTR3
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-37
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-8: Push-Pull PWM Mode – Master Duty Cycle and Independent Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-10: Push-Pull PWM Mode – Master Duty Cycle and Independent Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base*/
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Primary Time Base, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0100;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
Where:
PHASEx Phase of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
STPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
STPER
PHASE1 = 0
PHASE2
PHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
MDC
MDC
MDC
MDC
MDC
Complete
PWM1L Cycle
DTR1
ALTDTR1
ALTDTR2
DTR2
ALTDTR3
DTR3
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-38 © 2010-2011 Microchip Technology Inc.
Example 14-9: Push-Pull PWM Mode – Master Duty Cycle and Independent Phase, Fixed Secondary Period,
Edge-Aligned
Figure 14-11: Push-Pull PWM Mode – Independent Duty Cycles and Independent Periods, No Phase-Shifting,
Edge-Aligned
/* Set PWM Period on Secondary Time Base*/
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Secondary Time Base, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0108;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
PDC1
PDC2
PDC3
PHASE1
PHASE2
PHASE3
Start of
PWM Cycle Complete
PWM1L Cycle
Where:
PHASEx Period of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
DTRx Dead time for PWMxH Rising Edge
ALTDTRx Dead time for PWMxL Rising Edge
ALTDTR3
ALTDTR2
ALTDTR1 DTR1
DTR2
DTR3
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-39
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-10: Push-Pull PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Edge-Aligned
Figure 14-12: Push-Pull PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Edge-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1000;
PHASE2 = 900;
PHASE3 = 800;
/* Set Duty Cycles */
PDC1 = 200;
PDC2 = 300;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Independent Time Bases, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0200;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
PHASE1
PHASE2
PHASE3
Start of
PWM Cycle Complete
PWM1L Cycle
Where:
PHASEx Period of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
ALTDTR3
ALTDTR2
ALTDTR1 DTR1
DTR2
DTR3
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-40 © 2010-2011 Microchip Technology Inc.
Example 14-11: Push-Pull PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Edge-Aligned
Figure 14-13: Push-Pull PWM Mode – Independent Duty Cycles and Independent Periods, No Phase-Shifting,
Center-Aligned Mode
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1000;
PHASE2 = 900;
PHASE3 = 800;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Independent Time Bases, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0300;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
Start of
PWM Cycle
PHASE1
PHASE2
PHASE3
PDC1
PDC2
PDC2
PDC3
PDC3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Complete PWM1L
and PWM1H Cycle
Where:
PHASEx Period of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
DTRx Dead Time before PWMxH Falling Edge
ALTDTRx Dead Time before PWMxL Falling Edge
DTR1
ALTDTR1
DTR2
ALTDTR2
DTR3
ALTDTR3
PDC1
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-41
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-12: Push-Pull PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Center-Aligned Mode
Figure 14-14: Push-Pull PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Center-Aligned Mode
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1000;
PHASE2 = 900;
PHASE3 = 800;
/* Set Duty Cycles */
PDC1 = 200;
PDC2 = 300;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Independent Time Bases, Center-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0204;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
Where:
PHASEx Period of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
DTRx Dead Time before PWMxH Falling Edge
ALTDTRx Dead Time before PWMxL Falling Edge
Start of
PWM Cycle
PHASE1
PHASE2
PHASE3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Complete PWM1L
and PWM1H Cycle
DTR1
ALTDTR1
DTR2
ALTDTR2
DTR3
ALTDTR3
MDC
MDC
MDC
MDC
MDC
MDC
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-43
Section 14. High-Speed PWM
High-Speed PWM
14
14.6.2 Complementary PWM Mode
In Complementary PWM mode, the PWM output PWMxH is the complement of the PWMxL
output. Some typical applications of Complementary PWM mode are provided in
14.16 “Application Information”.
Figure 14-15 through Figure 14-22 and Example 14-14 through Example 14-21 show the PWM
outputs in multiple operating modes when the module operates in Complementary PWM mode.
Figure 14-15: Complementary PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Note: Not all of the features and registers listed in the Figures and Code Examples in this
section are available on all devices. Refer to the “High-Speed PWM” chapter of the
specific device data sheet for availability.
PTPER
PHASE1 = 0
PHASE2
PHASE3
PDC1
PDC2
PDC3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of PWM Cycle
Where: PHASEx Phase of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
PTPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
DTR1
DTR2
DTR3
ALTDTR1
ALTDTR2
ALTDTR3
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-44 © 2010-2011 Microchip Technology Inc.
Example 14-14: Complementary PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-16: Complementary PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base */
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
PDC1 = 150;
PDC2 = 200;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Complementary */
IOCON1 = IOCON2 = IOCON3 = 0xC000;
/* Set Primary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0000;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
STPER
PHASE1 = 0
PHASE2
PHASE3
PDC1
PDC2
PDC3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Where:
PHASEx Phase of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
STPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
DTR1
DTR2
DTR3
ALTDTR1
ALTDTR2
ALTDTR3
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-45
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-15: Complementary PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
Figure 14-17: Complementary PWM Mode – Master Duty Cycle and Independent Phase, Fixed Primary
Period, Edge-Aligned
/* Set PWM Period on Secondary Time Base */
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
PDC1 = 150;
PDC2 = 200;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Complementary */
IOCON1 = IOCON2 = IOCON3 = 0xC000;
/* Set Secondary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0008;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PTPER
PHASE1 = 0
PHASE2
PHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
MDC
Start of
PWM Cycle
Where:
PHASEx Phase of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
PTPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
DTR1
DTR2
DTR3
ALTDTR1
ALTDTR2
ALTDTR3
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-47
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-17: Complementary PWM Mode – Master Duty Cycle and Independent Phase, Fixed Secondary
Period, Edge-Aligned
Figure 14-19: Complementary PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Edge-Aligned
/* Set PWM Period on Secondary Time Base*/
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Complementary */
IOCON1 = IOCON2 = IOCON3 = 0xC000;
/* Set Secondary Time Base, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0108;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
PDC1
PDC2
PDC3
PHASE1
PHASE2
PHASE3
Start of
PWM Cycle
DTR1
DTR2
DTR3
ALTDTR1
ALTDTR2
ALTDTR3
Where:
PHASEx Period of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-48 © 2010-2011 Microchip Technology Inc.
Example 14-18: Complementary PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Edge-Aligned
Figure 14-20: Complementary PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Edge-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 800;
PHASE2 = 900;
PHASE3 = 1000;
/* Set Duty Cycles */
PDC1 = 200;
PDC2 = 300;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Complementary */
IOCON1 = IOCON2 = IOCON3 = 0xC000;
/* Set Independent Time Bases, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0200;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
PHASE1
PHASE2
PHASE3
Start of
PWM Cycle
DTR1
DTR2
DTR3
ALTDTR1
ALTDTR2
ALTDTR3
Where:
PHASEx Period of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-49
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-19: Complementary PWM Mode – Master Duty Cycles and Independent Periods, No
Phase-Shifting, Edge-Aligned
Figure 14-21: Complementary PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Center-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 800;
PHASE2 = 900;
PHASE3 = 1000;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Complementary */
IOCON1 = IOCON2 = IOCON3 = 0xC000;
/* Set Independent Time Bases, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0300;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PDC1
-ALTDTR1/2
PDC2
-ALTDTR2/2
PHASE1
PHASE2
PHASE3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Complete
PWM1H and
PWM1L Cycle
ALTDTR3/2
ALTDTR2/2
ALTDTR1/2 ALTDTR1/2
Where:
PHASEx Period of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
ALTDTRx Dead time for PWMxL
ALTDTR1/2
PDC3
-ALTDTR3/2
ALTDTR1/2
ALTDTR2/2
ALTDTR2/2
ALTDTR3/2
ALTDTR3/2
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-50 © 2010-2011 Microchip Technology Inc.
Example 14-20: Complementary PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Center-Aligned
Figure 14-22: Complementary PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Center-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1000;
PHASE2 = 900;
PHASE3 = 800;
/* Set Duty Cycles */
PDC1 = 400;
PDC2 = 300;
PDC3 = 200;
/* Set Dead Time Values */
/* DTRx Registers are ignored in this mode */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Complementary */
IOCON1 = IOCON2 = IOCON3 = 0xC000;
/* Set Independent Time Bases, Center-Aligned mode and
Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0204;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
MDC-
ALTDTR1/2
PHASE1
PHASE2
PHASE3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Complete
PWM1H and
PWM1L Cycle
ALTDTR3/2
ALTDTR2/2
ALTDTR1/2 ALTDTR1/2
Where:
PHASEx Period of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
ALTDTRx Dead time for PWMxL
ALTDTR1/2
MDC-
ALTDTR2/2
MDC-
ALTDTR3/2
ALTDTR1/2
ALTDTR2/2
ALTDTR2/2
ALTDTR3/2
ALTDTR3/2
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-51
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-21: Complementary PWM Mode – Master Duty Cycles and Independent Periods, No
Phase-Shifting, Center-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1000;
PHASE2 = 900;
PHASE3 = 800;
/* Set Duty Cycles */
MDC = 400;
/* Set Dead Time Values */
/* DTRx Registers are ignored in this mode */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Complementary */
IOCON1 = IOCON2 = IOCON3 = 0xC000;
/* Set Independent Time Bases, Center-Aligned mode and
Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0304;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-52 © 2010-2011 Microchip Technology Inc.
14.6.3 Redundant PWM Output Mode
In Redundant PWM Output mode, the High-Speed PWM module has the ability to provide two
copies of a single-ended PWM output signal per PWM pin pair (PWMxH, PWMxL). This mode
uses the PDCx register to specify the duty cycle. In this output mode, the two PWM output pins
will provide the same PWM signal unless the user-assigned application specifies an override
value. The following eight figures and examples show the Redundant PWM Output mode in
multiple operating modes.
Figure 14-23: Redundant PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Note: Not all of the features and registers listed in the Figures and Code Examples in this
section are available on all devices. Refer to the “High-Speed PWM” chapter of the
specific device data sheet for availability.
PTPER
PHASE1 = 0
PHASE2
PHASE3
PDC1
PDC2
PDC3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Where: PHASEx Phase of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
PTPER Period of PWMxH and PWMxL
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-53
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-22: Redundant PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-24: Redundant PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base */
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
PDC1 = 150;
PDC2 = 200;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Primary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0000;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
STPER
PHASE1 = 0
PHASE2
PHASE3
PDC1
PDC2
PDC3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Where:
PHASEx Phase of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
STPER Period of PWMxH and PWMxL
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-54 © 2010-2011 Microchip Technology Inc.
Example 14-23: Redundant PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
Figure 14-25: Redundant PWM Mode – Master Duty Cycle and Variable Phase, Fixed Primary Period,
Edge-Aligned
/* Set PWM Period on Secondary Time Base */
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
PDC1 = 150;
PDC2 = 200;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Secondary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0008;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PTPER
PHASE1 = 0
PHASE2
PHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
MDC
Start of
PWM Cycle
Where:
PHASEx Phase of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
PTPER Period of PWMxH and PWMxL
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-55
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-24: Redundant PWM Mode – Master Duty Cycle and Variable Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-26: Redundant PWM Mode – Master Duty Cycle and Variable Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base */
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
MDC = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Primary Time Base, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0100;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
STPER
PHASE1 = 0
PHASE2
PHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
MDC
Start of
PWM Cycle
Where:
PHASEx Phase of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
STPER Period of PWMxH and PWMxL
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-56 © 2010-2011 Microchip Technology Inc.
Example 14-25: Redundant PWM Mode – Master Duty Cycle and Variable Phase, Fixed Secondary Period,
Edge-Aligned
Figure 14-27: Redundant PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Edge-Aligned
/* Set PWM Period on Secondary Time Base */
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
MDC = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Secondary Time Base, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0108;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
PDC1
PDC2
PDC3
PHASE1
PHASE2
PHASE3
Start of
PWM Cycle
Where:
PHASEx Period of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-57
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-26: Redundant PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Edge-Aligned
Figure 14-28: Redundant PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Edge-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 800;
PHASE2 = 900;
PHASE3 = 1000;
/* Set Duty Cycles */
PDC1 = 200;
PDC2 = 300;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Independent Time Bases, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0200;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
PHASE1
PHASE2
PHASE3
Start of
PWM Cycle
Where:
PHASEx Period of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-58 © 2010-2011 Microchip Technology Inc.
Example 14-27: Redundant PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Edge-Aligned
Figure 14-29: Redundant PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Center-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 800;
PHASE2 = 900;
PHASE3 = 1000;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Independent Time Bases, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0300;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PDC1
PDC2
PDC3
PHASE1
PHASE2
PHASE3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Complete
PWM1H and
PWM1L Cycle
Where:
PHASEx Period of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-59
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-28: Redundant PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Center-Aligned
Figure 14-30: Redundant PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Center-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1000;
PHASE2 = 900;
PHASE3 = 800;
/* Set Duty Cycles */
PDC1 = 400;
PDC2 = 300;
PDC3 = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Independent Time Bases, Center-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0204;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
MDC
MDC
PHASE1
PHASE2
PHASE3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
Start of
PWM1H Cycle
Complete
PWM1H and
PWM1L Cycle
Where:
PHASEx Period of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-61
Section 14. High-Speed PWM
High-Speed PWM
14
14.6.4 True Independent PWM Output Mode
In True Independent PWM Output mode (PMOD = 11), the PWM outputs (PWMxH and PWMxL)
can have different duty cycles. The PDCx register specifies the duty cycle for the PWMxH output,
whereas the SDCx register specifies the duty cycle for the PWMxL output. In addition, the
PWMxH and PWMxL outputs can either have different periods or they can be phase-shifted
relative to each other.
• When ITB = 1, the PHASEx register specifies the PWM period for the PWMxH output and
the SPHASEx register specifies the PWM period for the PWMxL output
• When ITB = 0, the PHASEx register specifies the phase shift for the PWMxH output and
the SPHASEx register specifies the phase shift for the PWMxL output
Figure 14-31: Independent PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Note: Not all of the features and registers listed in the Figures and Code Examples in this
section are available on all devices. Refer to the “High-Speed PWM” chapter of the
specific device data sheet for availability.
Note: In Independent Time Base mode (ITB = 1), there may not be a deterministic phase
relationship between the PWMxH and PWMxL outputs.
PTPER
PHASE1 = 0
SPHASE1
PHASE2
SPHASE2
PHASE3
SPHASE3
PDC1
SDC1
PDC2
SDC2
PDC3
SDC3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Where: PHASEx Phase of PWMxH
SPHASEx Phase of PWMxL
PDCx Duty Cycle of PWMxH
SDCx Duty Cycle of PWMxL
PTPER Period of PWMxH and PWMxL
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-62 © 2010-2011 Microchip Technology Inc.
Example 14-30: Independent PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-32: Independent PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base */
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
SPHASE1 = 100;
PHASE2 = 200;
SPHASE2 = 300;
PHASE3 = 400;
SPHASE3 = 500;
/* Set Duty Cycles */
PDC1 = 100;
SDC1 = 200;
PDC2 = 300;
SDC2 = 400;
PDC3 = 500;
SDC3 = 600;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Independent */
IOCON1 = IOCON2 = IOCON3 = 0xCC00;
/* Set Primary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0000;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
STPER
PHASE1 = 0
SPHASE1
PHASE2
SPHASE2
PHASE3
SPHASE3
PDC1
SDC1
PDC2
SDC2
PDC3
SDC3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Where: PHASEx Phase of PWMxH
SPHASEx Phase of PWMxL
PDCx Duty Cycle of PWMxH
SDCx Duty Cycle of PWMxL
STPER Period of PWMxH and PWMxL
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-63
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-31: Independent PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
Figure 14-33: Independent PWM Mode – Master Duty Cycle, Variable Phase, Fixed Primary Period,
Edge-Aligned
/* Set PWM Period on Secondary Time Base */
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
SPHASE1 = 100;
PHASE2 = 200;
SPHASE2 = 300;
PHASE3 = 400;
SPHASE3 = 500;
/* Set Duty Cycles */
PDC1 = 100;
SDC1 = 200;
PDC2 = 300;
SDC2 = 400;
PDC3 = 500;
SDC3 = 600;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Independent */
IOCON1 = IOCON2 = IOCON3 = 0xCC00;
/* Set Secondary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0008;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PTPER
PHASE1 = 0
SPHASE1
PHASE2
SPHASE2
PHASE3
SPHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
MDC
MDC
MDC
MDC
Start of
PWM Cycle
Where: PHASEx Phase of PWMxH
SPHASEx Phase of PWMxL
MDC Duty Cycle of PWMxH and PWMxL
PTPER Period of PWMxH and PWMxL
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-64 © 2010-2011 Microchip Technology Inc.
Example 14-32: Independent PWM Mode – Master Duty Cycle, Variable Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-34: Independent PWM Mode – Master Duty Cycle, Variable Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base */
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
SPHASE1 = 100;
PHASE2 = 200;
SPHASE2 = 300;
PHASE3 = 400;
SPHASE3 = 500;
/* Set Duty Cycles */
MDC = 300;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Independent */
IOCON1 = IOCON2 = IOCON3 = 0xCC00;
/* Set Primary Time Base, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0100;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
STPER
PHASE1 = 0
SPHASE1
PHASE2
SPHASE2
PHASE3
SPHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
MDC
MDC
MDC
MDC
Start of
PWM Cycle
Where: PHASEx Phase of PWMxH
SPHASEx Phase of PWMxL
MDC Duty Cycle of PWMxH and PWMxL
STPER Period of PWMxH and PWMxL
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-66 © 2010-2011 Microchip Technology Inc.
Figure 14-35: Independent PWM Mode – Independent Duty Cycles and Periods, No Phase-Shifting,
Edge-Aligned
Example 14-34: Independent PWM Mode – Independent Duty Cycles and Periods, No Phase-Shifting,
Edge-Aligned
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
PDC1
SDC1
PDC2
SDC2
PDC3
SDC3
PHASE1
SPHASE1
PHASE2
SPHASE2
PHASE3
SPHASE3
Start of
PWM Cycle
Where: PHASEx Period of PWMxH
SPHASEx Period of PWMxL
PDCx Duty Cycle of PWMxH
SDCx Duty Cycle of PWMxL
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 800;
SPHASE1 = 900;
PHASE2 = 1000;
SPHASE2 = 1100;
PHASE3 = 1200;
SPHASE3 = 1300;
/* Set Duty Cycles */
PDC1 = 200;
SDC1 = 300;
PDC2 = 400;
SDC2 = 500;
PDC3 = 600;
SDC3 = 700;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Independent */
IOCON1 = IOCON2 = IOCON3 = 0xCC00;
/* Set Independent Time Bases, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0200;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-67
Section 14. High-Speed PWM
High-Speed PWM
14
Figure 14-36: Independent PWM Mode – Master Duty Cycles, Independent Periods, No Phase-Shifting,
Edge-Aligned
Example 14-35: Independent PWM Mode – Master Duty Cycles, Independent Periods, No Phase-Shifting,
Edge-Aligned
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
PHASE1
SPHASE1
PHASE2
SPHASE2
PHASE3
SPHASE3
Start of
PWM Cycle
Where: PHASEx Period of PWMxH
SPHASEx Period of PWMxL
MDC Duty Cycle of PWMxH and PWMxL
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 800;
SPHASE1 = 900;
PHASE2 = 1000;
SPHASE2 = 1100;
PHASE3 = 1200;
SPHASE3 = 1300;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Independent */
IOCON1 = IOCON2 = IOCON3 = 0xCC00;
/* Set Independent Time Bases, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0300;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-68 © 2010-2011 Microchip Technology Inc.
Figure 14-37: Independent PWM Mode – Independent Duty Cycles and Periods, No Phase-Shifting,
Center-Aligned
Example 14-36: Independent PWM Mode – Independent Duty Cycles and Periods, No Phase-Shifting,
Center-Aligned
PDC1
SDC1
PDC2
SDC2
PDC3
SDC3
PHASE1
SPHASE1
PHASE2
SPHASE2
PHASE3
SPHASE3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Complete
PWM1H Cycle
Where: PHASEx Period of PWMxH
SPHASEx Period of PWMxL
PDCx Duty Cycle of PWMxH
SDCx Duty Cycle of PWMxL
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1300;
SPHASE1 = 1200;
PHASE2 = 1100;
SPHASE2 = 1000;
PHASE3 = 900;
SPHASE3 = 800;
/* Set Duty Cycles */
PDC1 = 700;
SDC1 = 600;
PDC2 = 500;
SDC2 = 400;
PDC3 = 300;
SDC3 = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Independent */
IOCON1 = IOCON2 = IOCON3 = 0xCC00;
/* Set Independent Time Bases, Center-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0204;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-69
Section 14. High-Speed PWM
High-Speed PWM
14
Figure 14-38: Independent PWM Mode – Master Duty Cycles, Independent Periods, No Phase-Shifting,
Center-Aligned
Example 14-37: Independent PWM Mode – Master Duty Cycles, Independent Periods, No Phase-Shifting,
Center-Aligned
MDC
MDC
MDC
PHASE1
SPHASE1
PHASE2
SPHASE2
PHASE3
SPHASE3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
MDC
MDC
Start of
PWM1H Cycle
Complete
PWM1H Cycle
Where: PHASEx Period of PWMxH
SPHASEx Period of PWMxL
MDC Duty Cycle of PWMxH and PWMxL
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1300;
SPHASE1 = 1200;
PHASE2 = 1100;
SPHASE2 = 1000;
PHASE3 = 900;
SPHASE3 = 800;
/* Set Duty Cycles */
MDC = 700;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Independent */
IOCON1 = IOCON2 = IOCON3 = 0xCC00;
/* Set Independent Time Bases, Center-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0304;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-70 © 2010-2011 Microchip Technology Inc.
Table 14-3 lists the PWM register functionality for Independent Output mode.
Table 14-3: Independent Output Mode Register Functionality
Function
Configuration in PWMCONx Pins
MDCS ITB MTBS PWMxH PWMxL
PWM Duty Cycle 0xxPDCx SDCx
1xxMDC MDC
PWM Phase Shift x0xPHASEx SPHASEx
PWM Period xx0PTPER PTPER
xx1STPER STPER
x1xPHASEx SPHASEx
Legend: x = Don’t care
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-71
Section 14. High-Speed PWM
High-Speed PWM
14
14.7 PWM GENERATOR
This section describes the functionality of the PWM generator.
14.7.1 PWM Period
The PWM period value defines the switching frequency of the PWM pulses. The PWM period
value can be controlled by the Primary Master Time Base Period register (PTPER), or by the
Independent Time Period PHASEx and SPHASEx registers for the respective primary and
secondary PWM outputs, if available.
The PWM period value can be controlled in two ways when the High-Speed PWM module
operates in Independent Time Base mode:
• In some modes, the PHASEx register controls the PWM period value of the PWM output
signals (PWMxH and PWMxL)
• In True Independent Output mode, the PHASEx register controls the PWM period value of
the PWMxH output signal, and the SPHASEx register controls the PWM period value of the
PWMxL output signal
Refer to 14.6 “PWM Operating Modes”, for detailed information about various PWM modes and
their features.
When the High-Speed PWM module operates in Master Time Base mode, the PTPER register
holds the 16-bit value, which specifies the counting period for the PMTMR timer. When the
High-Speed PWM module operates in Independent Time Base mode, the PHASEx and
SPHASEx registers hold the 16-bit value that sp riod for the PTMRx andecifies the counting pe
STMRx timer, respectively. The timer period can be updated at any time by the user-assigned
application. The PWM time period (PTPER) in Edge-Aligned PWM mode (CAM bit
(PWMCONx<2>) is set to ‘0’) can be determined by using the Equation 14-1.
Equation 14-1: PERIOD, PHASEx and SPHASEx Register Value Calculation for
Edge-Aligned Mode
Based on Equation 14-1, while operating in the master time base (PTPER register) or the
independent time base (PHASEx and SPHASEx registers), the register value to be loaded is
shown in Example 14-38.
Example 14-38: PWM Time Period Calculation for Edge-Aligned Mode
Note: Not all registers and features listed in this section are available on all devices. Refer
to the “High-Speed PWM” chapter in the specific device data sheet for availability.
Where:
PTPER, PHASEx,
SPHASEx =
FPWM
* PWM Input Clock Prescaler
FOSC
FPWM = Desired PWM frequency
FOSC = Oscillator output (120 MHz for 60 MIPS)
PWM Input Clock Prescaler = Value defined in the PCLKDIV<2:0> bits (PTCON2<2:0)
PTPER 120MHz
20 1kHz ×
-------------------------- 6000= =
Where:
PWM Input Clock Prescaler = 1:1
System Oscillator Frequency (FOSC) = 120 MHz
Desired PWM Switching Frequency = 20 kHz
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-72 © 2010-2011 Microchip Technology Inc.
The PWM time period (PHASEx or SPHASEx) in Center-Aligned mode (CAM = 1 and ITB = 1),
can be determined using Equation 14-2. The PTPER register does not represent the period in
Center-Aligned mode, since this mode requires independent time bases, which are enabled by
setting ITB = 1.
Equation 14-2: PHASEx or SPHASEx Register Value Calculation in Center-Aligned
Mode
Based on Equation 14-2, when operating in independent time bases (PHASEx and SPHASEx
registers), the register value to be loaded is shown in Example 14-39.
Example 14-39: PWM Time Period Calculation Example in Center-Aligned Mode
The maximum available PWM period resolution is TOSC for Edge-Aligned mode and TOSC * 2 in
Center-Aligned mode. The PCLKDIV<2:0> bits (PTCON2<2:0>), determine the type of PWM
clock. The timer/counter is enabled or disabled by setting or clearing the PTEN bit
(PTCON<15>). The PMTMR timer can also be cleared using the PTEN bit.
If the EIPU bit (PTCON<10>) is set, the active master period register (an internal shadow
register) is updated immediately instead of waiting for the PWM cycle to end. The EIPU bit affects
the PMTMR master time base.
Example 14-40: Clock Prescaler Selection
Example 14-41: PWM Time Period Selection
Example 14-42: PWM Time Period Initialization
PHASEx, SPHASEx FOS C
FPWM PWM Input Clock Prescaler 2⋅ ⋅
-----------------------------------------------------------------------------------------------------=
PHASEx, SPHASEx 120 MHz
20 kHz 1 2⋅ ⋅
------------------------------------- 3000==
Where:
PWM Frequency (FPWM) = 20 kHz
PWM Input Clock Prescaler = 1:1
System Oscillator Frequency (FOSC) = 120 MHz
/* Select PWM time base input clock prescaler */
/* Choose divide ratio of 1:2 */
PTCON2bits.PCLKDIV = 1;
/* Select Time Base Period Control */
/* Choose one of these options */
PWMCON1bits.ITB = 0; /* PTPER provides the PWM time period value */
PWMCON1bits.ITB = 1; /* PHASEx/SPHASEx provides the PWM time period value */
/* Choose PWM time period based on FRC input clock */
/* PWM frequency is 100 kHz */
/* Choose one of the following options */
PTPER = 4808;
PHASEx = 4808;
SPHASEx = 4808;
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-73
Section 14. High-Speed PWM
High-Speed PWM
14
14.7.2 PWM Duty Cycle Control
The duty cycle determines the period of time the PWM output should remain in the active state.
Each duty cycle register allows a 16-bit duty cycle value to be specified. The duty cycle values
can be updated at any time by setting the IUE bit (PWMCONx<0>). If the IUE bit is ‘0’, the active
register updates at the start of the next PWM cycle.
The Master Duty Cycle register (MDC) enables multiple PWM generators to share a common
duty cycle register.The MDC register has an important role in Master Time Base mode.
In addition, each PWM generator has a Primary Duty Cycle register (PDCx) and on certain
devices, a Secondary Duty Cycle register (SDCx) that provides separate duty cycles to each
PWM.
14.7.2.1 MASTER DUTY CYCLE (MDC)
The master time base generator controls the master duty cycle. The MDCS bit (PWMCONx<8>),
determines whether the duty cycle of each of the PWMxH and PWMxL outputs are controlled by
the PWM Master Duty Cycle register (MDC) or the PWM Primary Duty Cycle (PDCx) and PWM
Secondary Duty Cycle (SDCx) registers.
The MDC register enables sharing of the common duty cycle register among multiple PWM
generators and saves the CPU overhead required in updating multiple duty cycle registers.
14.7.2.2 PRIMARY DUTY CYCLE (PDCx)
The independent time base controls the primary duty cycle when the ITB bit (PWMCONx<9>) is
set to ‘1’. The PDCx register is an input register that provides the duty cycle value for the primary
PWM output signal (PWMxH).
Figure 14-39: Primary Duty Cycle Comparison
PDCx Register
PMTMR
Compare Logic PWMx Signal
0
15
15
MUX
MDC Register
MDCS Select
0 1
CLK
15
0
0
<=
Note: In Independent Output mode, PDCx affects PWMxH only.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-74 © 2010-2011 Microchip Technology Inc.
14.7.2.3 SECONDARY DUTY CYCLE (SDCx)
The independent time base in the PWMCONx register controls the Secondary Duty Cycle
register (SDCx) when the ITB bit is set to ‘1’. The SDCx register is an input register that provides
the duty cycle value for the secondary PWM output signal (PWMxL).
Figure 14-40: Secondary Duty Cycle Comparison
The duty cycle can be determined by using Equation 14-3.
Equation 14-3: MDC, PDCx and SDCx Calculation
Based on Equation 14-3, when the master, independent primary, or independent secondary duty
cycle is used, the register value SDCx register, respectively.is loaded in the MDC, PDCx, or
Note: The SDCx register is not available on all devices. Refer to the “High-Speed PWM”
chapter of the specific device data sheet for availability.
Note 1: If a duty cycle value is greater than or equal to the period value, a signal will have
a duty cycle of 100 percent.
2: When dead time compensation is disabled if PDCx does not adhere to (PDCx >
((ALTDTRx/2) -1)) the PWMxH will be constantly high.
3: If PDCx > (ALTDTRx + DTRx - 1) condition is not satisfied it could result in one or
both of the below:
a) Loss of dead time.
b) PWMxH will be constantly high.
SDCx Register
STMRx
Compare Logic PWMx Signal
015
15
MUX
MDC Register
MDCS Select
0 1
Clk
15
0
0
<=
Note: In Independent Output mode, SDCx affects PWMxL only.
MDC, PDCx, and SDCx FOSC
FPWM PWM Input Clock Prescaler⋅
------------------------------------------------------------------------------------------- Desired Duty Cycle⋅=
Where:
FPWM = PWM Frequency
FOSC = System Oscillator Output
PWM Input Clock Prescaler = Value defined in the PCLKDIV<2:0> bits (PTCON<2:0>)
Desired Duty Cycle = Value between 0 and 1 for desired duty cycle
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-76 © 2010-2011 Microchip Technology Inc.
14.7.3 Dead Time Generation
The dead time refers to a programmable period of time (specified by the PWM Dead Time
register (DTRx) or the PWM Alternate Dead Time register (ALTDTRx)), which prevents a PWM
output from being asserted until its complementary PWM signal has been deasserted for the
specified time.
The High-Speed PWM module has four dead time control units. Each dead time control unit has
its own dead time value.
Dead time generation can be provided when any of the PWM I/O pin pairs are operating in
Complementary Output mode. Many power converter circuits require dead time because power
transistors cannot switch instantaneously. To prevent current shoot-through, some amount of
time must be provided between the turn-off event of one PWM output and the turn-on event of
the other PWM output in a complementary pair or the turn-on event of the other transistor.
The High-Speed PWM module provides positive as well as negative dead time. The positive
dead time prevents overlapping of PWM outputs. Positive dead time generation is available for
all output modes. Positive dead time circuitry works by blanking (gating) the leading edge of the
PWM signal. Negative dead time is the forced overlap of the PWMxH and PWMxL signals.
Negative dead time works when the extended time period of the currently active PWM output
overlaps the PWM output that is just asserted. Certain converter techniques require a limited
amount of current shoot-through.
Negative dead time is specified only for complementary PWM signals. Negative dead time does
not apply to user or current-limit, or fault overrides. This mode can be implemented by using
phase shift values in the PHASEx registers that shifts the PWM outputs so that the outputs
overlap another PWM signal from a different PWM output channel. Negative dead time is only
implemented for Edge-Aligned mode (CAM = 0).
The dead time logic acts as a gate and allows an asserted PWM signal or an override value to
propagate to the output. The dead time logic never asserts a PWM output on its own initiative.
Figure 14-41: Dual Dead Time Waveforms for Edge-Aligned Mode
PWMxH
PWMxL
PWMxH
PWMxL
PWMxH
PWMxL
DTRx ALTDTRx
No dead time
Period Period
Positive dead time
Negative dead time
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-77
Section 14. High-Speed PWM
High-Speed PWM
14
Figure 14-42: Dual Dead Time Waveforms for Center-Aligned Mode
The dead time feature can be disabled for each PWM generator. The dead time functionality is
controlled by the DTC<1:0> bits (PWMCONx<7:6>).
14.7.4 Dead Time Generators
Each complementary output pair for the High-Speed PWM module has a 12-bit down counter to
produce the dead time insertion. Each dead time unit has a rising and falling edge detector
connected to the duty cycle comparison output. Depending on whether the edge is rising or
falling, one of the transitions on the complementary outputs is delayed until the associated dead
time timer generates the specific delay period.
The dead time logic monitors the rising and falling edges of the PWM signals. The dead time
counters reset when the associated PWM signal is inactive, and start counting when the PWM
signal is active. Any selected signal source that provides the PWM output signal is processed by
the dead time logic.
The dead time can be determined using the formula shown in Equation 14-6.
Equation 14-6: Dead Time Calculation
Three Dead Time Control modes are available, which are described in the following sections.
PWMxH
PWMxL
PWMxH
PWMxL
ALTDTRx
No dead time
Period Period
Positive dead time
ALTDTRx/2
Note: Dual dead times are not allowed in Center-Aligned mode.
Negative dead time is not supported in Center-Aligned mode.
ALTDTRx, DTRx = FOSC
PWM Input Clock Prescaler
Desired Dead Time
*
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-78 © 2010-2011 Microchip Technology Inc.
14.7.4.1 POSITIVE DEAD TIME
The Positive Dead Time mode describes a period of time when both PWMxH and PWMxL
outputs are not asserted. This mode is useful when the application designer needs to allocate
time to disable some power transistors prior to enabling other transistors. This is similar to a
“Break before Make” switch. When Positive Dead Time mode is specified in Edge-Aligned PWM
mode (CAM = 0), the DTRx register specifies the dead time for the PWMxH output, and the
ALTDTRx register specifies the dead time for the PWMxL output. When Center-Aligned mode is
enabled (CAM = 1), the ALTDTR register specifies the dead time, while the DTRx register is
ignored. These two modes are shown in Figure 14-43 and Figure 14-44.
Figure 14-43: Positive Dead Time in Edge-Aligned Mode and Complementary Mode
Figure 14-44: Positive Dead Time in Center-Aligned Mode and Complementary Mode
14.7.4.2 NEGATIVE DEAD TIME
The Negative Dead Time mode describes a period of time when both PWMxH and PWMxL
outputs are asserted. This mode is useful in current fed topologies that need to provide a path
for current to flow when the power transistors are switching. This is similar to a “Make before
Break” switch. When Negative Dead Time mode is specified in Edge-Aligned mode, the DTRx
register specifies the negative dead time for the PWMxL output, and the ALTDTRx register
specifies the negative dead time for the PWMxH output. When Center-Aligned mode is enabled
(CAM = 1), negative dead time is not supported, and the ALTDTRx and DTRx registers are
ignored. This mode is shown in Figure 14-45.
Figure 14-45: Negative Dead Time in Edge-Aligned Mode and Complementary Mode
PWMxH
PWMxL
Start of
PWM Cycle
DTRx
PDCx or MDC
ALTDTRx
Period Register (PTPER,
STPER or PHASEx)
PWMxH
PWMxL
Start of
PWM Cycle
PDCx or MDC
-ALTDTRx/2
Period Register (PTPER,
STPER or PHASEx)
ALTDTRx/2
Complete PWMxH
and PWMxL Cycle
ALTDTRx/2
ALTDTRx/2ALTDTRx/2
PWMxH
PWMxL
Start of
PWM Cycle
DTRx
PDCx or MDC
ALTDTRx
Period Register (PTPER,
STPER or PHASEx)
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-79
Section 14. High-Speed PWM
High-Speed PWM
14
14.7.4.3 DEAD TIME COMPENSATION
When dead time is applied to the PWM signals in AC motor control applications, the transistors
are disabled. During dead time, motor current continues to flow through the free-wheeling
diodes, but the applied voltage is zero. The zero applied voltage during dead time causes a
distortion of the desired voltage waveform and subsequently a motor current distortion. This
distortion causes torque variations that can affect the stability of the control system, and the
performance of the motor.
Dead Time Compensation mode enables an external signal (DTCMPx) to modify the duty cycle
to overcome motor current distortion caused by the dead time.
When Dead Time Compensation mode is selected via the DTC<1:0> bits (PWMCONx<7:6>), an
external input signal (DTCMPx) will cause the value in the DTRx register to be added to, or
subtracted from, the duty cycle specified by the PDCx or MDC registers. The ALTDTRx register
will specify the dead time for both the PWMxH and PWMxL output signals.
Dead time compensation is available only for Complementary PWM output mode with Positive
Dead Time mode. Negative dead times or any other PWM output mode are not supported by
Dead Time Compensation mode.
Figure 14-46: Dead Time Compensation in Edge-Aligned Mode (DTCMPx Pin = 0 and DTCP = 0 or DTCMPx
Pin = 1 and DTCP = 1)
PWMxH
PWMxL
Start of
PWM Cycle
PDCx
DTRx
PDCx – DTRx
ALTDTRx = 0
PDCx – DTRx
– ALTDTRx
ALTDTRx ALTDTRx
PWMxH
PWMxL
PWMxH
PWMxL
Period Register (PTPER, STPER or PHASEx)
DTRx = 0
ALTDTRx = 0
DTRx 0
ALTDTRx = 0
DTRx ≠ 0
ALTDTRx ≠ 0
≠
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-80 © 2010-2011 Microchip Technology Inc.
Figure 14-47: Dead Time Compensation in Edge-Aligned Mode (DTCMPx Pin = 1 and DTCP = 0 or DTCMPx
Pin = 0 and DTCP = 1)
PWMxH
PWMxL
Start of
PWM Cycle
PDCx
Period Register (PTPER, STPER or PHASEx)
DTRx
PDCx + DTRx
ALTDTRx = 0
PDCx + DTRx
– ALTDTRx
ALTDTRx ALTDTRx
PWMxH
PWMxL
PWMxH
PWMxL
DTRx = 0
ALTDTRx = 0
DTRx ≠ 0
ALTDTRx = 0
DTRx ≠ 0
ALTDTRx ≠ 0
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-81
Section 14. High-Speed PWM
High-Speed PWM
14
Figure 14-48: Dead Time Compensation in Center-Aligned Mode (DTCMPx Pin = 0 and DTCP = 0 or DTCMPx
Pin = 1 and DTCP = 1)
PWMxH
PWMxL
Start of
PWM Cycle
PDCx
DTRx
PDCx – DTRx
ALTDTRx = 0
PWMxH
PWMxL
PWMxH
PWMxL
Period Register PHASEx
Complete PWMxH and PWMxL Cycle
ALTDTRx/2 ALTDTRx/2
PDCx – DTRx
– ALTDTRx/2
DTRx = 0
ALTDTRx = 0
DTRx ≠ 0
ALTDTRx = 0
DTRx ≠ 0
ALTDTRx ≠ 0
ALTDTRx/2
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-82 © 2010-2011 Microchip Technology Inc.
Figure 14-49: Dead Time Compensation in Center-Aligned Mode (DTCMPx Pin = 1 and DTCP = 0 or DTCMPx
Pin = 0 and DTCP = 1)
The dead time compensation external input control signal, DTCMPx, is sampled at the beginning
of each dead time period. This sampling process ensures that the control signal does not change
midway through the dead time generation process. The DTCMPx signal determines whether the
duty cycle will be increased or decreased by the amount specified in the DTRx register.
14.7.4.4 DEAD TIME DISABLED
The dead time logic can be disabled per PWM generator. The dead time functionality is controlled
by the DTC<2:0> bits (PWMCONx<7:6>).
DTRx = 0
ALTDTRx = 0
DTRx ≠ 0
ALTDTRx = 0
DTRx ≠ 0
ALTDTRx ≠ 0
PWMxH
PWMxL
Start of
PWM Cycle
PDCx
DTRx
PWMxH
PWMxL
PWMxH
PWMxL
Period Register PHASEx
Complete PWMxH and PWMxL Cycle
ALTDTRx/2 ALTDTRx/2
PDCx + DTRx
-ALTDTRx/2 ALTDTRx/2
PDCx + DTRx
ALTDTRx = 0
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-83
Section 14. High-Speed PWM
High-Speed PWM
14
14.7.5 Dead Time Ranges
The dead time duration provided by each dead time unit is set by specifying an unsigned value
in the DTRx and ALTDTRx registers. At maximum operating clock frequency with a T OSC duty
cycle resolution, the dead time resolution is TOSC (7.14 ns at 140 MHz of FOSC). The maximum
dead time value is (2 14 – 1)TOSC = 116.9 µs when operating at 140 MHz FOSC.
14.7.6 Dead Time Distortion
For duty cycle values near 0% or 100%, the PWM signal becomes nonlinear if dead time is
active. For any duty cycle value less than the dead time, the PWM output is zero. For duty
cycle values greater than “100% – dead time”, the PWM output is the same as if the duty cycle
is “100% – dead time”.
14.7.7 Dead Time Insertion in Center-Aligned Mode
While using Center-Aligned mode and complementary PWM, only the ALTDTRx register should
be used for dead time insertion. The dead time is inserted in the PWM waveform as shown in
Figure 14-50.
Figure 14-50: Positive Dead Time Insertion in Center-Aligned Mode
PWMxH
PWMxL
Start of
PWM Cycle
PDCx or MDC
- ALTDTRx/2
Period Register (PTPER,
STPER or PHASEx)
ALTDTRx/2
Complete PWMxH
and PWMxL Cycle
ALTDTRx/2
PDCx or MDC
Period Register (PTPER,
STPER or PHASEx)
0
ALTDTRx/2
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-84 © 2010-2011 Microchip Technology Inc.
14.7.8 Phase Shift
Phase shift is the relative offset between PWMxH or PWMxL with respect to the master time
base. In Independent Output mode, the PHASEx register determines the relative phase shift
between PWMxH and the master time base. The SPHASEx register determines the relative
phase shift between PWMxL and the master time base. The contents of the PHASEx register are
used as an initialization value for the PTMRx register, and the SPHASEx register contents are
used as an initialization value for the STMRx register.
Figure 14-51 and Figure 14-52 provide example waveforms for phase shifting in Complementary
mode and Independent Output mode, respectively.
Figure 14-51: Phase Shifting (Complementary Mode)
Figure 14-52: Phase Shifting (Independent Output Mode)
In addition, there are two shadow registers for the PHASEx and SPHASEx registers that are
updated whenever new values are written by the user-assigned application. These values are
transferred from the shadow registers to the PHASEx and SPHASEx registers on an
independent time base Reset. The actual application of these phase offsets on the PWM output
will occur on a master time base Reset.
Note: The SPHASEx register is not available on all devices. Refer to the “High-Speed
PWM” chapter in the specific device data sheet for availability.
PWMxH without Phase Shift
PWMxH with Phase Shift
PWMxL without Phase Shift
PWMxL with Phase Shift
PHASEx
PWMxH without Phase Shift
PWMxH with Phase Shift
PWMxL without Phase Shift
PWMxL with Phase Shift
(Different Duty Cycle)
PHASEx
SPHASEx
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-85
Section 14. High-Speed PWM
High-Speed PWM
14
Figure 14-53 shows the timing diagram that illustrates how these events are generated.
The phase offset value can be any value between zero and the value in the PTPER register. Any
PHASEx or SPHASEx value greater than the PERIOD value will be treated as a value equal to
the Period. It is not possible to create phase shifts greater than the Period.
Figure 14-53: Phase Shift Waveforms
Master Time Base
(PMTMR)
Period Match
Requested PHASEx
PHASEx
SPHASEx
PTMRx
PWMxH
STMRx SDCx
PDCx
50 75 25
50 75 25
Note: Operation of the High-Speed PWM module with independent time base is controlled by the master time base.
PTPER = 100
PMTMR rollover on PTPER match
Next Phase Next Phase
Load on ITB rollover
Load ITB with PHASEx
on MTB rollover
0
PWMxL
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-86 © 2010-2011 Microchip Technology Inc.
Example 14-45: PWM Phase Shift Initialization
The bit resolution of PWM duty cycle, phase, and dead time with respect to different input clock
prescaler selections are shown in Table 14-5.
Table 14-4: Duty Cycle, Phase, Dead Time Bit Resolution vs. Prescaler Selection
PWM Clock
Prescaler
Bit Resolution
64 * Tosc 32 * Tosc 16 * Tosc 8 * Tosc 4 * Tosc 2 * Tosc Tosc
1:1 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
1:2 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 —
1:4 bit 4 bit 3 bit 2 bit 1 bit 0 — —
1:8 bit 3 bit 2 bit 1 bit 0 — — —
1:16 bit 2 bit 1 bit 0 — — — —
1:32 bit 1 bit 0 — — — — —
1:64 bit 0 — — — — — —
/* Initialize phase shift value for the PWM output */
/* Phase shifts are initialized when operating in Master Time Base */
PHASEx = 100; /* Primary phase shift value */
SPHASEx = 100; /* Secondary phase shift value */
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-87
Section 14. High-Speed PWM
High-Speed PWM
14
14.8 PWM TRIGGER
For the ADC module, the TRIGx register specifies the triggering point for the PWMxH and
PWMxL outputs, respectively. An ADC trigger signal will be generated when the independent
time base counter (PTMRx) register value matches with the specified TRIGx register value.
The TRGDIV<3:0> bits in the TRGCONx register act as a postscaler for the TRIGx register to
generate ADC triggers. This allows the trigger signal to the ADC to be generated once for every
1, 2, 3.... and 16 trigger events. These bits specify how frequently the ADC trigger is generated.
Each PWM generator has TRGSTRT<5:0> bits (TRGCONx<5:0>) that specify how many PWM
cycles to wait before generating the first ADC trigger.
Figure 14-54 shows the logic for ADC triggering by the High-Speed PWM module.
Figure 14-54: PWM Trigger for Analog-to-Digital Conversion
Depending on the settings of the TRGDIV<3:0> and TRGSTRT<5:0> bits, triggers are generated
at different PWM intervals, as shown in Figure 14-55 through Figure 14-62.
Figure 14-55: PWM Trigger Signal in Relation to the PWM Output in Edge-Aligned Mode
(TRGDIV = 0, TRGSTRT = 0)
PTMRx
TRIGx
1:1
.
.
1:16
PWMx Trigger to ADC
TRGSTRT
Clock
.
Delay TRGDIV
PWM Trigger Interrupt
CMP
Note: A trigger can only be generated on the first PWM interval when the TRGDIV<3:0>
bits are set to ‘0’.
PWMxH
TRIGx = 0
TRIGx = 8
TRIGx = 4808
TRIGx = 9616
1
PTPER = 9616
62 3 4 5 7
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-88 © 2010-2011 Microchip Technology Inc.
Figure 14-56: PWM Trigger Signal in Relation to the PWM Output in Edge-Aligned Mode
(TRGDIV = 0, TRGSTRT = 1)
Figure 14-57: PWM Trigger Signal in Relation to the PWM Output in Edge-Aligned Mode
(TRGDIV = 0, TRGSTRT = 2)
PWMxH
TRIGx = 0
TRIGx = 8
TRIGx = 4808
TRIGx = 9616
1
PTPER = 9616
62 3 4 5 7
PWMxH
TRIGx = 0
TRIGx = 8
TRIGx = 4808
TRIGx = 9616
1
PTPER = 9616
2 3 4 5
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-89
Section 14. High-Speed PWM
High-Speed PWM
14
Figure 14-58: PWM Trigger Signal in Relation to the PWM Output in Edge-Aligned Mode
(TRGDIV = 1, TRGSTRT = 0)
Figure 14-59: PWM Trigger Signal in Relation to the PWM Output in Edge-Aligned Mode
(TRGDIV = 1, TRGSTRT = 1)
PWMxH
TRIGx = 0
TRIGx = 8
TRIGx = 4808
TRIGx = 9616
PTPER = 9616
51 2 3 4 6
PWMxH
TRIGx = 0
TRIGx = 8
TRIGx = 4808
TRIGx = 9616
1
PTPER = 9616
62 3 4 5 7
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-90 © 2010-2011 Microchip Technology Inc.
Figure 14-60: PWM Trigger Signal in Relation to the PWM Output in Edge-Aligned Mode
(TRGDIV = 2, TRGSTRT = 0)
Figure 14-61: PWM Trigger Signal in Relation to the PWM Output in Edge-Aligned Mode
(TRGDIV = 2, TRGSTRT = 2)
PWMxH
TRIGx = 0
TRIGx = 8
TRIGx = 4808
TRIGx = 9616
1
PTPER = 9616
62 3 4 5 7
PWMxH
TRIGx = 0
TRIGx = 8
TRIGx = 4808
TRIGx = 9616
1
PTPER = 9616
53 4 6 7
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-91
Section 14. High-Speed PWM
High-Speed PWM
14
Figure 14-62: PWM Trigger Signal in Relation to the PWM Output in Edge-Aligned Mode
(TRGDIV = 2, TRGSTRT = 3)
Figure 14-63: Trigger Signal in Relation to PWM Output in Center-Aligned Mode (TRGDIV = 0, TRGSTRT = 0)
Figure 14-64: Trigger Signal in Relation to PWM Output in Center-Aligned Mode (TRGDIV = 0, TRGSTRT = 1)
PWMxH
TRIGx = 0
TRIGx = 8
TRIGx = 4808
TRIGx = 9616
1
PTPER = 9616
64 5 7 8 910 11
1 2PWMxH
TRIGx = 0
TRIGx = 500
TRIGx = 250
TRIGx = 750
TRIGx = 1000
PDCx = 500
PHASEx = PTPER = 1000
3 4
12PWMxH
TRIGx = 0
TRIGx = 500
TRIGx = 250
TRIGx = 750
TRIGx = 1000
PDCx = 500
PHASEx = PTPER = 1000
34
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-92 © 2010-2011 Microchip Technology Inc.
Figure 14-65: Trigger Signal in Relation to PWM Output in Center-Aligned Mode (TRGDIV = 0, TRGSTRT = 2)
Figure 14-66: Trigger Signal in Relation to PWM Output in Center-Aligned Mode (TRGDIV = 1, TRGSTRT = 0)
Figure 14-67: Trigger Signal in Relation to PWM Output in Center-Aligned Mode (TRGDIV = 1, TRGSTRT = 1)
The trigger divider allows the user-assigned application to tailor the ADC sample rates to the
requirements of the control loop.
If ADC triggers are generated at a rate faster than the rate that the ADC can process, the
operation may result in loss of some samples. However, the user-assigned application can
ensure that the time it provides is enough to complete an ADC operation within a single PWM
cycle.
12PWMxH
TRIGx = 0
TRIGx = 500
TRIGx = 250
TRIGx = 750
TRIGx = 1000
PDCx = 500
PHASEx = PTPER = 1000
34
1 2PWMxH
TRIGx = 0
TRIGx = 500
TRIGx = 250
TRIGx = 750
TRIGx = 1000
PDCx = 500
PHASEx = PTPER = 1000
34
12PWMxH
TRIGx = 0
TRIGx = 500
TRIGx = 250
TRIGx = 750
TRIGx = 1000
PDCx = 500
PHASEx = PTPER = 1000
34
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-93
Section 14. High-Speed PWM
High-Speed PWM
14
The trigger pulse is generated regardless of the state of the TRGIEN bit (PWMCONx<10>). If the
TRGIEN bit (PWMCONx<10>) is set to ‘1’, an interrupt request is generated.
Example 14-46: Independent PWM ADC Triggering
Note 1: The TRGSTAT bit is only cleared by clearing the TRGIEN bit. It is not cleared
automatically.
2: Dynamic triggering can show some advantages where multiple PWM channels are
used in applications, such as IPFC and multi-phase buck regulators. The TRIGx
values can be changed based on the PWM period, duty, load current, etc. This is
to ensure that the trigger points are separated from the rise and fall instances of the
PWM channel.
/* Independent PWM ADC Triggering */
TRIG1 = 1248; /* Point at which the ADC module is to be
triggered by primary PWM */
TRGCON1bits.TRGDIV = 0; /* Trigger output divider set to trigger ADC on
every trigger match event */
TRGCON1bits.TRGSTRT = 4; /* First ADC trigger event occurs after four
trigger match events */
PWMCON1bits.TRGIEN = 1; /* Trigger event generates an interrupt request */
while (PWMCON1bits.TRGSTAT = = 1); /* Wait for ADC interrupt status change */
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-94 © 2010-2011 Microchip Technology Inc.
Figure 14-68: Effect of Phase Shift on PWM Triggers
When phase shifting the PWM signal, the PWM timer value is updated to reflect the new phase
value. There is a possibility of missing trigger events when changing the phase from a smaller
value to a larger value. The user-assigned application must ensure that this does not affect any
control loop execution.
Timing diagrams that show triggers based on multiple PWM time base configurations are
provided in Figure 14-63 through Figure 14-67.
PTPER = 100
Master
Time Base
(PMTMR)
Requested
PHASEx
PMTMR rollover on PTPER match
Next Phase Next Phase
(EIPU = 0) (EIPU = 0)
Load PTMRx with PHASEx
on PMTMR rollover
Load PTMRx with PHASEx
on PMTMR rollover
Load PTMRx with PHASEx
on PMTMR rollover
PTMRx = 50
PTMRx = 75
PTMRx = 50
PTMRx = 75
PTPER = 100
50
50
75 25
75 25
PHASEx
PWM Timer
PTMRx
Trigger event is missed
when PHASEx is increased
60
60
TRIGx = 60
PTMRx = 25
Load PHASEx on PTMRx rollover Load PHASEx on PTMRx rollover
60
TRIGx = 60 TRIGx = 60
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-96 © 2010-2011 Microchip Technology Inc.
Figure 14-71: Independent PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned, Trigger Using PWM Generator
Figure 14-72: Independent PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned, Trigger Using PWM Generator
PTPER
PHASE1
SPHASE1
SDC1
PWM1H
PWM1L
Start of
PWM Cycle
Where:
PHASE1 Phase of PWM1H
SPHASE1 Phase of PWM1L
PDC1 Duty Cycle of PWM1H
SDC1 Duty Cycle of PWM1L
PTPER Period of PWM1H, PWM1L and Trigger
TRIG1 Special Event Compare
PDC1
Trigger
TRIG1
STPER
PHASE1
SPHASE1
SDC1
PWM1H
PWM1L
Start of
PWM Cycle
Where:
PHASE1 Phase of PWM1H
SPHASE1 Phase of PWM1L
PDC1 Duty Cycle of PWM1H
SDC1 Duty Cycle of PWM1L
STPER Period of PWM1H, PWM1L and Trigger
TRIG1 Special Event Compare
PDC1
Trigger
TRIG1
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-97
Section 14. High-Speed PWM
High-Speed PWM
14
Figure 14-73: Independent PWM Mode – Independent Duty Cycle and Period, No Phase Shifting,
Edge-Aligned, Trigger Using PWM Generator
Table 14-6 provides a summary of the registers used as period and compare values for ADC
triggers at different PWM configurations.
Table 14-5: ADC Triggers
PWM1H
PWM1L
PDC1
SDC1
PHASE1
SPHASE1
Start of
PWM Cycle
Where:
PHASE1 Period of PWM1H and Trigger
SPHASE1 Period of PWM1L
PDC1 Duty Cycle of PWM1H
SDC1 Duty Cycle of PWM1L
TRIG1 Special Event Compare
Trigger
TRIG1 TRIG1
ADxCON1 (1) PWMCONx Function
SSRCG SSRC ITB MTBS ADC Trigger Period ADC Trigger Event
0 011 x x PTPER SEVTCMP
0 101 x x STPER SSEVTCMP
1 000 0 0 PTPER TRIG1
1 000 0 1 STPER TRIG1
1 000 1 x PHASE1 TRIG1
1 001 0 0 PTPER TRIG2
1 001 0 1 STPER TRIG2
1 001 1 x PHASE2 TRIG2
1 010 0 0 PTPER TRIG3
1 010 0 1 STPER TRIG3
1 010 1 x PHASE3 TRIG3
1 011 0 0 PTPER TRIG4
1 011 0 1 STPER TRIG4
1 011 1 x PHASE4 TRIG4
1 100 0 0 PTPER TRIG5
1 100 0 1 STPER TRIG5
1 100 1 x PHASE5 TRIG5
1 101 0 0 PTPER TRIG6
1 101 0 1 STPER TRIG6
1 101 1 x PHASE6 TRIG6
1 110 0 0 PTPER TRIG7
1 110 0 1 STPER TRIG7
1 110 1 x PHASE7 TRIG7
Legend: x = don’t care
Note 1: Refer to Section 16. “Analog-to-Digital Converter (ADC)” (DS70621) for more
information about ADC Configuration registers.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-98 © 2010-2011 Microchip Technology Inc.
14.9 PWM INTERRUPTS
The High-Speed PWM module can generate interrupts based on internal timing signals or
external signals through the current-limit and fault inputs. The primary time base module can
generate an interrupt request when a specified event occurs. Each PWM generator module
provides its own interrupt request signal to the interrupt controller. The interrupt for each PWM
generator is a Boolean OR of the trigger event interrupt request, the current-limit input event, or
the fault input event for that module.
Besides one interrupt request signal per PWM generator, the interrupt controller receives an
interrupt request signal from the primary time base on special events.
The interrupt requests coming from each PWM generator are called Individual PWM Interrupts.
The Interrupt Request (IRQ) for each one of these individual interrupts can come from the PWM
individual trigger, PWM fault logic, or PWM current-limit logic. Each PWM generator has the
PWM interrupt flag in an IFSx register. When an interrupt request is generated by any of the
above sources, the PWM interrupt flag associ M generator is set.ated with the selected PW
If more than one IRQ source is enabled, the interrupt source is determined using the
user-assigned application by checking the TRGSTAT, FLTSTAT and CLSTAT bits in the
PWMCONx register.
To configure interrupts, the application software should first clear the interrupt flags, enable the
interrupts (see the PTCON ( ), STCON (Register 14-1 Register 14-4), and PWMCONx
(Register 14-12) registers), and finally, enable the PWM module.
14.9.1 PWM Time Base Interrupts
In each PWM generator, the High-Speed PWM module can generate interrupts based on the
master time base and/or the individual time base. The PWM Special Event Compare register
(SEVTCMP) specifies timer based interrupts for the primary time base, and the TRIGx registers
specify timer based interrupts for the individual time bases.
The primary time base special event interrupt is enabled via the SEIEN bit (PTCON<11>). In
each PWM generator, the individual time base interrupts generated by the trigger logic are
controlled by the TRGIEN bit (PWMCON<10>).
Note: To enable PWM interrupts, use the initialization procedure defined in Section 6.
“Interrupts” (DS70600) of the “dsPIC33E/PIC24E Family Reference Manual”,
which is available from the Microchip Web site (www.microchip.com).
Note: When an appropriate match condition occurs, the Special Event Trigger signal and
the individual PWM trigger pulses to the ADC are always generated regardless of
the setting of their respective interrupt enable bits.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-100 © 2010-2011 Microchip Technology Inc.
Figure 14-74: PWM Fault Control Module Block Diagram
14.10.2 PWM Fault Generated by the Analog Comparator
The dsPIC33E/PIC24E devices support virtual (internal) connections to the output of the
comparator modules CxOUT (see Figure 26-1 in Section 26.0 “Comparator Module”
(DS70357).
Virtual connections provide a simple way of inter-peripheral connection without utilizing a
physical pin. For example, by setting the FLT1R<6:0> bits of the RPINR12 register to the value
of 'b0000001, the output of the Analog Comparator, C1OUT, will be connected to the PWM
Fault 1 input, which allows the Analog Comparator to trigger PWM faults without the use of an
actual physical pin on the device.
Example 14-47 shows the configuration of the Analog Comparator 1 as one of the fault sources
to the PWM that is connected to the fault input pin 1.
Example 14-47: Configuring Analog Comparator 1 as a Fault Source to the HS PWM
Module
FLTSRC<4:0>
Fault
0
1
PWMxH, PWMxL
2
PWM
Generator
FLTDAT<1:0> 2
PWMxH, PWMxL Signals 2
Fault
Mode
Selection
Logic
FLTMOD<1:0>
Latch
Clear
FLTSTAT
PMTMR
Number
Input
FLTx
CxOUT
__builtin_write_OSCCONL(OSCCON & (~(1<<6))); // Unlock Register
RPINR12bits.FLT1R = 1;// Assign FLT1 to Pin C1OUT
__builtin_write_OSCCONL(OSCCON | (1<<6));// Lock Registers
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-101
Section 14. High-Speed PWM
High-Speed PWM
14
14.10.3 Fault Interrupts
The FLTIENx bit (PWMCONx<12>) determine whether an interrupt will be generated when the
FLTx input is asserted high. The FLTDAT<1:0> (High/Low) bits supply the data values to be
assigned to the PWMxH and PWMxL pins in case of a fault.
The PWM Fault states are available on the FLTSTAT bit (PWMCONx<15>). The FLTSTAT bit
displays the fault IRQ latch. If fault interrupts are not enabled, the FLTSTAT bit displays the status
of the selected FLTx input in positive logic format. When the fault input pins are not used in
association with a PWM generator, these pins can be used as general purpose I/O or interrupt
input pins.
In addition to its operation as the PWM logic, the fault pin logic can also operate as an external
interrupt pin. If the faults are not allowed to affect the PWM generators in the FCLCONx register,
the fault pin can be used as a general purpose interrupt pin.
14.10.3.1 FAULT INPUT PIN MODES
The fault input pin has two modes of operation:
• Latched mode: In Latched mode, the PWM outputs follow the states defined in the FLTDAT
bits in the IOCONx registers when the fault pin is asserted. The PWM outputs remain in this
state until the fault pin is deasserted and the corresponding interrupt flag has been cleared in
software. When both of these actions have occurred, the PWM outputs return to normal
operation at the beginning of the next PWM cycle boundary. If the FLTSTAT bit
(PWMCONx<15>) is cleared before the Fault condition ends, the High-Speed PWM module
waits until the fault pin is no longer asserted. Software can clear the FLTSTAT bit by writing ‘0’
to the FLTIEN bit in the PWMCONx register.
• Cycle-by-Cycle mode: In Cycle-by-Cycle mode, the PWM outputs remain in the deasserted
PWM state as long as the fault input pin remains asserted. In Complementary PWM Output
mode, PWMxH is low (deasserted) and PWMxL is high (asserted). After the fault pin is driven
high, the PWM outputs return to normal operation at the beginning of the following PWM
cycle.
The operating mode for each fault input pin is selected by using the FLTMOD bits
(FCLCONx<1:0>).
14.10.4 Fault Entry
With respect to the device clock signals, the PWM pins always provide asynchronous response
to the fault input pins. Therefore, if ‘0’ is deasserted, the FLTDAT bit will immediately deassert
the associated PWM output, and if the specified FLTDAT bits are asserted (set to ‘1’), the
FLTDAT bits are processed by the dead time logic prior to being output as a PWM signal.
Refer to 14.12.4 “Fault/Current-Limit Override and Dead Time Logic”, for more information
on data sensitivity and behavior in response to current-limit or fault events.
14.10.5 Fault Exit
After a Fault condition has ended, the PWM signals must be restored at a PWM cycle boundary
to ensure proper synchronization of PWM signal edges and manual signal overrides. The next
PWM cycle begins when the PTMR value is zero.
If Cycle-by-Cycle Fault mode is selected, the fault is automatically reset on every PWM cycle. No
additional coding is needed to exit the Fault condition.
For the Latched Fault mode, however, the following sequence must be followed to exit the Fault
condition:
1. Poll the PWM fault source to determine, if the fault signal has been deasserted.
2. If the PWM fault interrupt is not enabled, skip the following sub-steps and proceed to
step 3. If the PWM fault interrupt is enabled, perform the following sub-steps, and then
proceed to step 4.
a) Complete the PWM fault Interrupt Service Routine.
b) Disable the PWM fault interrupt by clearing the FLTIEN bit (PWMCONx <12>).
c) Enable the PWM fault interrupt by setting FLTMOD<1:0> (FCLCONx <1:0>) = 0b00.
3. Disable PWM faults by setting FLTMOD<1:0> (FCLCONx <1:0>) = 0b11.
4. Enable the latched PWM Fault mode by setting FLTMOD<1:0> (FCLCONx <1:0>) = 0b00.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-103
Section 14. High-Speed PWM
High-Speed PWM
14
Figure 14-75: PWM Current-Limit Control Circuit Logic Diagram
14.10.9 Current-Limit Interrupts
The state of the PWM current-limit conditions is available on the CLSTAT bit (PWMCONx<14>).
The CLSTAT bits display the current-limit IRQ flag if the CLIEN bit is set. If current-limit interrupts
are not enabled, the CLSTAT bits display the status of the selected current-limit inputs in positive
logic format. When the current-limit input pin associated with a PWM generator is not used, these
pins can be used as general purpose I/O or interrupt input pins.
The current-limit pins are normally active-high. If set to ‘1’, the CLPOL bit (FCLCONx<9>) invert
the selected current-limit input signal and drives the signal into active-low state.
The interrupts generated by the selected current-limit signals are combined to create a single
interrupt request signal. This signal is sent to the interrupt controller, which has its own interrupt
vector, interrupt flag bit, interrupt enable bit, and interrupt priority bits associated with it.
The fault pins are also readable through the port I/O logic when the High-Speed PWM module is
enabled. This capability allows the user-assigned application to poll the state of the fault pins in
software.
14.10.10 Simultaneous PWM Faults and Current-Limits
The current-limit override function, if enabled and active, forces the PWMxH and PWMxL pins to
read the values specified by the CLDAT<1:0> bits (IOCONx<3:2>), unless the fault function is
enabled and active. If the selected fault input is active, the PWMxH and PWMxL outputs read the
values specified by the FLTDAT<1:0> bits (IOCONx<5:4>).
CLSRC<4:0>
FLTx
CxOUT
0
1
PWMxH, PWMxL
2
PWM
Generator #
CLDAT<1:0> 2
PWMxH, PWMxL Signals 2
Cycle-by-Cycle
Mode
PMTMR
CLMOD
EN
Fault
Input
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-104 © 2010-2011 Microchip Technology Inc.
14.10.11 PWM Fault and Current-Limit Trigger Outputs to ADC
The current-limit and fault source selection bits, CLSRC<4:0> (FCLCONx<14:10>) and
FLTSRC<4:0> (FCLCONx<7:3>), control the fault selection to each PWM generator module. The
control multiplexers select the desired fault and current-limit signals for their respective modules.
Example 14-48: PWM Fault, Current-Limit and Leading-Edge Blanking Configuration
/* PWM Fault, Current-Limit and Leading-Edge Blanking Configuration */
FCLCON1bits.IFLTMOD = 0;
/*
CLDAT bits control PWMxH and FLTDAT bits control PWMxL
*/
FCLCON1bits.CLSRC = 8; /* Current-limit input source is Analog Comparator 1 */
FCLCON1bits.FLTSRC = 9; /* Fault input source is Analog Comparator 2 */
FCLCON1bits.CLPOL = 1; /* Current-limit source is active-low */
FCLCON1bits.FLTPOL = 1; /* Fault Input source is active-low */
FCLCON1bits.CLMOD = 1; /* Enable current-limit function */
FCLCON1bits.FLTMOD = 1; /* Enable Cycle-by-Cycle Fault mode */
IOCON1bits.FLTDAT = 0; /* PWMxH and PWMxL are driven inactive on occurrence of fault */
IOCON1bits.CLDAT = 0;
/*
PWMxH and PWMxL are driven inactive on occurrence of current-limit
*/
LEBCON1bits.PHR = 1; /* Rising edge of PWMxH will trigger LEB counter */
LEBCON1bits.PHF = 0; /* Falling edge of PWMxH is ignored by LEB counter */
LEBCON1bits.PLR = 1; /* Rising edge of PWMxL will trigger LEB counter */
LEBCON1bits.PLF = 0; /* Falling edge of PWMxL is ignored by LEB counter */
LEBCON1bits.FLTLEBEN = 1; /* Enable fault LEB for selected source */
LEBCON1bits.CLLEBEN = 1; /* Enable current-limit LEB for selected source */
LEBDLY1bits.LEB = 8; /* Blank for a period (8 x Tosc) */
PWMCON1bits.XPRES = 0; /* External pins do not affect PWM time base reset */
PWMCON1bits.FLTIEN = 1; /* Enable fault interrupt */
PWMCON1bits.CLIEN = 1; /* Enable current-limit interrupt */
while (PWMCON1bits.FLTSTAT == 1); /* Wait when fault interrupt is pending */
while (PWMCON1bits.CLSTAT == 1);
/*
Wait when current-limit interrupt is pending
*/
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-105
Section 14. High-Speed PWM
High-Speed PWM
14
14.11 SPECIAL FEATURES
The following special features are available in the High-Speed PWM module:
• Leading-Edge Blanking (LEB)
• State Blanking
• Chop mode
• Individual time base capture
• PWM pin swapping
• PWM output pin control and override
• PWM immediate update
14.11.1 Leading-Edge Blanking (LEB)
Each PWM generator supports LEB of the current-limit and fault inputs configured using the
LEBCONx and LEBDLYx bits in the Leading-Edge Blanking Control registers. The purpose of
LEB is to mask the transients that occur on the application printed circuit board when the power
transistors are turned ON and OFF.
The LEB bits are edge-sensitive. These bits support the blanking (ignoring) of the current-limit
and fault inputs for a period of 0 to (4095 * T OSC) following any specified rising or falling edge of
the PWMxH and PWMxL signals.
Equation 14-7: Leading-Edge Blanking Calculation
In high-speed switching applications, switches (such as MOSFETs and IGBTs) typically generate
very large transients. These transients can cause measurement errors. The LEB function
enables the user-assigned application to ignore the expected transients caused by the
MOSFETs/IGBTs switching that occurs near the edges of the PWM output signals.
The PHR, PHF, PLR and PLF bits of the LEBCONx register select the edge type of the PWMxH
and PWMxL signals, which starts the blanking timer. If a new selected edge triggers the LEB
timer while the timer is still active from a previously selected PWM edge, the timer reinitializes
and continues counting.
The FLTLEBEN and CLLEBEN bits enable the application of the blanking period to the selected
fault and current-limit inputs. Figure 14-76 illustrates how an application ignores the fault signal
in the specified blanking period.
Figure 14-76: Leading-Edge Blanking
LEB Duration at Maximum Clock Rate = (LEBDLYx<11:0>) * TOSC
Switching Noise
Blanking time is determined by the
LEB<9:3> bits in the LEBCONx registers
Fault and current-limit
circuitry ignores the
switching noise
PWM Output
High Power Signal
Blanking Signal
Power signal as seen
by fault circuitry
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-106 © 2010-2011 Microchip Technology Inc.
14.11.2 State Blanking
Each PWM generator supports state blanking where it is possible to specify conditions where the
current-limit and/or Fault signal is entirely ignored. The BCH, BCL, BPHH, BPHL, BPLH, and
BPLL bits in the LEBCONx registers select any combination of the PWMxH, PWMxL, and CHOP
clock signals as the source of the state blanking function.
The selected Fault or current-limit signal can be ignored when either the PWMxH or PWMxL
output is high or low. In addition, the BLANKSEL<3:0> bits (AUXCONx<11:9>) can be used to
select another PWM generator as the blanking signal source.
Figure 14-77: State Blanking Logic Diagram
14.11.3 Chop Mode
Many power control applications use transistor configurations that require an isolated transistor
gate drive. An example is a three-phase “H-bridge” configuration, where the upper transistors are
at an elevated electrical potential.
One method to achieve an isolated gate drive circuit is to use pulse transformers to couple the
PWM signals across a galvanic isolation barrier to the transistors. Unfortunately, in applications
that use either long duty cycle ratios, or slow PWM frequencies, the transformer’s low-frequency
response is poor. The pulse transformer cannot pass a long duration PWM signal to the isolated
transistor(s). If the PWM signals are “chopped” or gated by a high-frequency clock signal, the
high-frequency alternating signal easily passes through the pulse transformer. The chopping
frequency is typically hundreds or thousands of times higher in frequency as compared to the
PWM frequency. The higher the chopping (carrier) frequency relative to the PWM frequency, the
more the PWM duty cycle resolution is preserved.
PWMxH
BPHL
PWMxL
BPHH
BPLL
BPLH
BCL
State blanking active
Any blanking active
BCH
Polarity adjusted
selected current-limit
input signal
Selected blank signal
BLANKSEL<3:0> Polarity adjusted
selected Fault
input signal
Blanking-modified
Fault signal
Blanking-modified
current-limit signal
No blanking active
Blanking from LEB circuit
PWM1H
PWM2H
PWM3H
PWM4H
PWM9H
MUX
(AUXCONx<11:9>)

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Modell: dsPIC33EV64GM106

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