Használati útmutató Microchip DSPIC33EP64MC204

Microchip nincs kategorizálva DSPIC33EP64MC204

Olvassa el alább 📖 a magyar nyelvű használati útmutatót Microchip DSPIC33EP64MC204 (130 oldal) a nincs kategorizálva kategóriában. Ezt az útmutatót 4 ember találta hasznosnak és 2 felhasználó értékelte átlagosan 4.5 csillagra

Letöltés PDF
Oldal 1/130
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-1
High-Speed PWM
14
Section 14. High-Speed PWM
HIGHLIGHTS
This section of the manual contains the following major topics:
14.1 Introduction .................................................................................................................. 14-2
14.2 Features....................................................................................................................... 14-2
14.3 Control Registers ......................................................................................................... 14-3
14.4 Architecture Overview................................................................................................ 14-24
14.5 Module Description .................................................................................................... 14-27
14.6 PWM Operating Modes.............................................................................................. 14-33
14.7 PWM Generator......................................................................................................... 14-71
14.8 PWM Trigger.............................................................................................................. 14-87
14.9 PWM Interrupts.......................................................................................................... 14-98
14.10 PWM Fault Pins ......................................................................................................... 14-99
14.11 Special Features ...................................................................................................... 14-105
14.12 PWM Output Pin Control...........................................................................................14-111
14.13 Immediate Update of PWM Duty Cycle ................................................................... 14-113
14.14 Power-Saving Modes............................................................................................... 14-114
14.15 External Control of Individual Time Base(s)............................................................. 14-114
14.16 Application Information ............................................................................................ 14-115
14.17 Register Map............................................................................................................ 14-126
14.18 Related Application Notes........................................................................................ 14-127
14.19 Revision History ....................................................................................................... 14-128
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-2 © 2010-2011 Microchip Technology Inc.
14.1 INTRODUCTION
This section describes the High-Speed Pulse-Width Modulator (PWM) module and its
associated operational modes. The High-Speed PWM module in the dsPIC33E/PIC24E
device family supports a wide variety of PWM modes and is ideal for power
conversion/motor control applications. Some of the common applications include:
• AC-to-DC converters
• DC-to-DC converters
• AC and DC motors: BLDC, PMSM, ACIM, SRM, etc.
• Inverters
• Battery chargers
• Digital lighting
• Uninterrupted Power Supply (UPS)
• Power Factor Correction (PFC) (e.g., Interleaved PFC and Bridgeless PFC)
14.2 FEATURES
The High-Speed PWM module consists of the following major features:
• Up to seven PWM generators, each with an individual time base
• Two PWM outputs per PWM generator
• Individual period and duty cycle for each PWM output
• Duty cycle, dead time, phase shift and frequency resolution equal to the system clock
source (TOSC)
• Independent fault and current-limit inputs for up to 14 PWM outputs
• Redundant Output mode
• Independent Output mode (this feature is not available on all devices)
• Push-Pull Output mode
• Complementary Output mode
• Center-Aligned PWM mode
• Output override control
• Special Event Trigger
• PWM capture feature
• Prescaler for input clock
• ADC triggering with PWM
• Independent PWM frequency, duty cycle and phase shift changes
• Leading-Edge Blanking (LEB) functionality
• Dead time compensation
• Output clock chopping
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33E/PIC24E devices.
Please consult the note at the beginning of the “High-Speed PWM” chapter in the
current device data sheet to check whether this document supports the device you
are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-3
Section 14. High-Speed PWM
High-Speed PWM
14
14.3 CONTROL REGISTERS
The following registers control the operation of the High-Speed PWM module:
•PTCON: PWM Time Base Control Register
- Enables or disables the High-Speed PWM module
- Sets the Special Event Trigger for the ADC
- Enables or disables immediate period updates
- Selects the synchronizing source for the master time base
- Specifies synchronization settings
•PTCON2: PWM Clock Divider Select Register 2
Provides the clock prescaler to the PWM master time base
•PTPER: Primary Master Time Base Period Register
Provides the PWM time period value
•STCON: PWM Secondary Master Time Base Control Registe (1)
- Enables or disables immediate period updates based on the secondary master time base
- Selects the synchronization source for the secondary master time base
- Specifies the synchronization setting for secondary master time base control
• STCON2: PWM Secondary Clock Divider Select Register 2(1)
Provides the clock prescaler to the PWM secondary master time base
•STPER: Secondary Master Time Base Period Register(1)
Provides the secondary master time base period value
•MDC: PWM Master Duty Cycle Register
Provides the PWM master duty cycle value
•SEVTCMP: PWM Special Event Compare Register
Provides the compare value that is used to trigger the ADC module
•SSEVTCMP: PWM Secondary Special Event Compare Register(1)
Provides the compare value that is used to trigger the ADC module based on the
secondary master time base
•CHOP: PWM Chop Clock Generator Register
- Provides the chop clock frequency
- Enables or disables the chop clock generator
•PWMKEY: PWM Unlock Register(1)
Writes the unlock sequence to allow writes to the IOCONx and FCLCONx registers
•PWMCONx: PWM Control Register
- Enables or disables fault interrupt, current-limit interrupt and primary trigger interrupt
- Provides the interrupt status for fault interrupt, current-limit interrupt and primary trigger
interrupt
- Selects the type of time base (master time base or independent time base)
- Selects the type of duty cycle (master duty cycle or independent duty cycle)
- Controls Dead Time mode
- Enables or disables Center-Aligned mode
- Controls the external PWM Reset operation
- Enables or disables immediate updates of the duty cycle, phase offset, independent time
base period
•IOCONx: PWM I/O Control Register
- Enables or disables PWM pin control feature (PWM control or GPIO)
- Controls fault/current limit override values
- Enables PWMxH and PWMxL pin swapping
- Controls the PWMxH and PWMxL output polarity
- Controls the PWMxH and PWMxL output if any of the following modes is selected:
• Complementary mode
• Push-Pull mode
• True Independent mode
Note: Not all registers are available on all devices. Refer to the “High-Speed PWM”
chapter in the specific device data sheet for availability.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-6 © 2010-2011 Microchip Technology Inc.
Register 14-2: PTCON2: PWM Clock Divider Select Register 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PCLKDIV<2:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide by 64
101 = Divide by 32
100 = Divide by 16
011 = Divide by 8
010 = Divide by 4
001 = Divide by 2
000 = Divide by 1, maximum PWM timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
Register 14-3: PTPER: Primary Master Time Base Period Register
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PTPER<15:8>(1)
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
PTPER<7:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits(1)
Note 1: 1 LSb = 1 Tosc. For example, 7.14 ns for 70 MIPS operation.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-7
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-4: STCON: PWM Secondary Master Time Base Control Registe (1)
U-0 U-0 U-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — SESTAT SEIEN EIPU(2) SYNCPOL SYNCOEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SYNCEN SYNCSRC<2:0> SEVTPS<3:0>
bit 7 bit 0
Legend: HC = Cleared in Hardware HS = Set in Hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Secondary Special Event Interrupt is pending
0 = Secondary Special Event Interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Secondary Special Event Interrupt is enabled
0 = Secondary Special Event Interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(2)
1 = Active Secondary Period register is updated immediately
0 = Active Secondary Period register updates occur on PWM cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit
1 = SYNCO2 output is active-low
0 = SYNCO2 output is active-high
bit 8 SYNCOEN: Secondary Master Time Base Sync Enable bit
1 = SYNCO2 output is enabled
0 = SYNCO2 output is disabled
bit 7 SYNCEN: External Secondary Master Time Base Synchronization Enable bit
1 = External synchronization of secondary time base is enabled
0 = External synchronization of secondary time base is disabled
bit 6-4 SYNCSRC<2:0>: Secondary Time Base Sync Source Selection bits
These bits select the SYNCIx or PTGOx input as the synchronous source. Refer to the “High-Speed
PWM” chapter in the specific device data sheet for availability.
bit 3-0 SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits
1111 = 1:16 Postscale
•
•
•
0001 = 1:2 Postscale
0000 = 1:1 Postscale
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
2: This bit only applies to the secondary master time base period.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-8 © 2010-2011 Microchip Technology Inc.
Register 14-5: STCON2: PWM Secondary Clock Divider Select Register 2
(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PCLKDIV<2:0>(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(2)
111 = Reserved
110 = Divide by 64
101 = Divide by 32
100 = Divide by 16
011 = Divide by 8
010 = Divide by 4
001 = Divide by 2
000 = Divide by 1, maximum PWM timing resolution (power-on default)
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-9
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-6: STPER: Secondary Master Time Base Period Register
(1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
STPER<15:8>
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
STPER<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 STPER<15:0>: Secondary Master Time Base Period Value bits
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
Register 14-7: MDC: PWM Master Duty Cycle Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 MDC<15:0>: Master PWM Duty Cycle Value bits
Register 14-8: SEVTCMP: PWM Special Event Compare Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SEVTCMP<15:0>: Special Event Compare Count Value bits
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-10 © 2010-2011 Microchip Technology Inc.
Register 14-9: SSEVTCMP: PWM Secondary Special Event Compare Register
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEVTCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEVTCMP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SSEVTCMP<15:0>: Secondary Special Event Compare Count Value bits
The optional SSEVTCMP register and the optional secondary master time base provide an additional
Special Event Trigger. The secondary special event trigger also has its own postscaler controlled by
the SEVTPS<3:0> bits in the STCON register.
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
Register 14-10: CHOP: PWM Chop Clock Generator Register
R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
CHPCLKEN — — — — — CHOPCLK<9:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHOPCLK<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CHPCLKEN: Enable Chop Clock Generator bit
1 = Chop clock generator is enabled
0 = Chop clock generator is disabled
bit 14-10 Unimplemented: Read as ‘0’
bit 9-0 CHOPCLK<9:0>: Chop Clock Divider bits
Chop Frequency = (FP/PLKDIV) / (CHOPCLK<9:0> + 1)
As an example, for devices running at 60 MIPS, a value of all zeros will yield a 60 MHz chop clock
(period = 16.7 ns) with the PWM clock prescaler configured for fastest clock. A value of ‘0000000001’
in the CHOPCLK<9:0> bits will yield a 30 MHz chop clock with the PWM clock prescaler configured
for fastest clock.
Note: The chop clock generator operates with the Primary PWM Clock Prescaler bits (PCLKDIV<2:0>) in the
PTCON2 register.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-11
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-11: PWMKEY: PWM Unlock Register(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWMKEY<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWMKEY<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PWMKEY<15:0>: PWM Unlock bits
If the PWMLOCK Configuration bit is asserted (PWMLOCK = 1), the IOCONx and FCLCONx registers
are writable only after the proper sequence is written to the PWMKEY register. If the PWMLOCK
Configuration bit is deasserted (PWMLOCK = 0), the IOCONx and FCLCONx registers are writable at
all times. Refer to 14.5.3 “Write Protection” for further details of the unlock sequence.
Note 1: This register is implemented only in devices where the PWMLOCK Configuration bit is present in the
FOSCSEL Configuration register.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-12 © 2010-2011 Microchip Technology Inc.
Register 14-12: PWMCONx: PWM Control Register
HS/HC-0 HS/HC-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTSTAT(1) CLSTAT(1) TRGSTAT FLTIEN CLIEN TRGIEN ITB(3) MDCS(3)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
DTC<1:0> DTCP(5) — MTBS CAM(2,3) XPRES(4) IUE(3)
bit 7 bit 0
Legend: HC = Cleared in Hardware HS = Set in Hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FLTSTAT: Fault Interrupt Status bit(1)
1 = Fault interrupt is pending
0 = No fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
bit 14 CLSTAT: Current-Limit Interrupt Status bit(1)
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
bit 13 TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
bit 12 FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
bit 11 CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt enabled
0 = Current-limit interrupt disabled and the CLSTAT bit is cleared
bit 10 TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared
bit 9 ITB: Independent Time Base Mode bit
(3)
1 = PHASEx/SPHASEx registers provide time base period for this PWM generator
0 = PTPER register provides timing for this PWM generator
bit 8 Master Duty Cycle MDCS: Register Select bit(3)
1 = MDC register provides duty cycle information for this PWM generator
0 = PDCx and SDCx registers provide duty cycle information for this PWM generator
Note 1: Software must clear the interrupt status here, and in the corresponding IFS bit in the Interrupt Controller.
2: The Independent Time Base mode (ITB = 1 0) must be enabled to use Center-Aligned mode. If ITB = , the
CAM bit is ignored.
3: These bits should not be changed after the PWM is enabled (PTEN = 1).
4: To operate in External Period Reset mode, the ITB bit must be set to ‘ ’ and the CLMOD bit in the 1
FCLCONx register must be set to ‘0’.
5: For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored.
6: Negative dead time is only implemented for Edge-Aligned mode (CAM = 0).
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-13
Section 14. High-Speed PWM
High-Speed PWM
14
bit 7-6 DTC<1:0>: Dead Time Control bits
11 = Dead Time Compensation mode enabled
10 = Dead time function is disabled
01 = Negative dead time actively applied for Complementary Output mode(6)
00 = Positive dead time actively applied for all output modes
bit 5 DTCP: Dead Time Compensation Polarity bit(5)
1 = If DTCMPx pin = 0, PWMxL is shortened, and PWMxH is lengthened
If DTCMPx pin = 1, PWMxH is shortened, and PWMxL is lengthened
0 = If DTCMPx pin = 0, PWMxH is shortened, and PWMxL is lengthened
If DTCMPx pin = 1, PWMxL is shortened, and PWMxH is lengthened
bit 4 Unimplemented: Read as ‘0’
bit 3 MTBS: Master Time Base Select bit
1 = PWM generator uses the secondary master time base for synchronization and the clock source
for the PWM generation logic (if secondary time base is available)
0 = PWM generator uses the primary master time base for synchronization and the clock source for
the PWM generation logic
bit 2 CAM: Center-Aligned Mode Enable bit(2,3)
1 = Center-Aligned mode is enabled
0 = Edge-Aligned mode is enabled
bit 1 External PWM Reset Control bitXPRES: (4)
1 = Current-limit source resets primary local time base for this PWM generator if it is in Independent
Time Base mode
0 = External pins do not affect PWM time base
bit 0 IUE: Immediate Update Enable bit(3)
1 = Updates to the active MDC/PDCx/SDCx/DTRx/ALTDTRx/PHASEx/SPHASEx registers are
immediate
0 = Updates to the active MDC/PDCx/SDCx/DTRx/ALTDTRx/PHASEx/SPHASEx registers are
synchronized to the PWM time base
Register 14-12: PWMCONx: PWM Control Register (Continued)
Note 1: Software must clear the interrupt status here, and in the corresponding IFS bit in the Interrupt Controller.
2: The Independent Time Base mode (ITB = 1 0) must be enabled to use Center-Aligned mode. If ITB = , the
CAM bit is ignored.
3: These bits should not be changed after the PWM is enabled (PTEN = 1).
4: To operate in External Period Reset mode, the ITB bit must be set to ‘ ’ and the CLMOD bit in the 1
FCLCONx register must be set to ‘0’.
5: For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored.
6: Negative dead time is only implemented for Edge-Aligned mode (CAM = 0).
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-14 © 2010-2011 Microchip Technology Inc.
Register 14-13: IOCONx: PWM I/O Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OVRDAT<1:0> FLTDAT<1:0>(1,2) CLDAT<1:0> SWAP OSYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PENH: PWMxH Output Pin Ownership bit
1 = PWM module controls PWMxH pin
0 = GPIO module controls PWMxH pin
bit 14 PENL: PWMxL Output Pin Ownership bit
1 = PWM module controls PWMxL pin
0 = GPIO module controls PWMxL pin
bit 13 POLH: PWMxH Output Pin Polarity bit
1 = PWMxH pin is active-low
0 = PWMxH pin is active-high
bit 12 POLL: PWMxL Output Pin Polarity bit
1 = PWMxL pin is active-low
0 = PWMxL pin is active-high
bit 11-10 PMOD<1:0>: PWM # I/O Pin Mode bits
11 = PWM I/O pin pair is in True Independent PWM Output mode
(3)
10 = PWM I/O pin pair is in Push-Pull Output mode
01 = PWM I/O pin pair is in Redundant Output mode
00 = PWM I/O pin pair is in Complementary Output mode
bit 9 OVRENH: Override Enable for PWMxH Pin bit
1 = OVRDAT<1> provides data for output on PWMxH pin
0 = PWM generator provides data for PWMxH pin
bit 8 OVRENL: Override Enable for PWMxL Pin bit
1 = OVRDAT<0> provides data for output on PWMxL pin
0 = PWM generator provides data for PWMxL pin
bit 7-6 OVRDAT<1:0>: State(2) for PWMxH, PWMxL Pins if Override is Enabled bits
If OVERENH = 1, OVRDAT<1> provides data for PWMxH
If OVERENL = 1, OVRDAT<0> provides data for PWMxL
Note 1: These bits must not be changed after the PWM module is enabled (PTEN = 1).
2: State represents Active/Inactive state of the PWM, depending on the POLH and POLL bits. For example, if
FLTDAT<1> is set to ‘1’ and POLH is set to ‘1’, the PWMxH pin will be at logic level 0 (active level) when a
fault occurs.
3: This feature is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific device
data sheet for availability.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-15
Section 14. High-Speed PWM
High-Speed PWM
14
bit 5-4 FLTDAT<1:0>: State(2) for PWMxH and PWMxL Pins if FLTMOD is Enabled bits(1)
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If fault is active, FLTDAT<1> provides the state for PWMxH.
If fault is active, FLTDAT<0> provides the state for PWMxL.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:
If current-limit is active, FLTDAT<1> provides the state for PWMxH.
If fault is active, FLTDAT<0> provides the state for PWMxL.
bit 3-2 CLDAT<1:0>: State(2) for PWMxH and PWMxL Pins if CLMOD is Enabled bits
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If current-limit is active, CLDAT<1> provides the state for PWMxH.
If current-limit is active, CLDAT<0> provides the state for PWMxL.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:
The CLDAT<1:0> bits are ignored.
bit 1 SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to PWMxL pin; PWMxL output signal is connected to PWMxH
pin
0 = PWMxH and PWMxL output signals pins are mapped to their respective pins
bit 0 OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base
0 = Output overrides via the OVRDAT<1:0> bits occur on next CPU clock boundary
Register 14-13: IOCONx: PWM I/O Control Register (Continued)
Note 1: These bits must not be changed after the PWM module is enabled (PTEN = 1).
2: State represents Active/Inactive state of the PWM, depending on the POLH and POLL bits. For example, if
FLTDAT<1> is set to ‘1’ and POLH is set to ‘1’, the PWMxH pin will be at logic level 0 (active level) when a
fault occurs.
3: This feature is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific device
data sheet for availability.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-16 © 2010-2011 Microchip Technology Inc.
Register 14-14: FCLCONx: PWM Fault Current-Limit Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFLTMOD(4) CLSRC<4:0>(2,3) CLPOL(1) CLMOD
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTSRC<4:0>(2,3) FLTPOL(1) FLTMOD<1:0>(4)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IFLTMOD: Independent Fault Mode Enable bit
(4)
1 = Independent Fault mode: Current-limit input maps FLTDAT<1> to PWMxH output, and fault input
maps FLTDAT<0> to PWMxL output. The CLDAT<1:0> bits are not used for override functions.
0= Normal Fault mode: Current-limit and fault inputs map CLDAT<1:0> and FLTDAT<1:0> to PWMxH
and PWMxL outputs.
bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select bits for PWM Generator #
(2,3)
These bits specify the current-limit control signal source. Refer to the “High-Speed PWM” chapter of
the specific device data sheet for available selections.
bit 9 CLPOL: Current-Limit Polarity bit for PWM Generator #(1)
1 = The selected current-limit source is active-low
0 = The selected current-limit source is active-high
bit 8 CLMOD: Current-Limit Mode Enable bit for PWM Generator #
1 = Current-Limit mode is enabled
0 = Current-Limit mode is disabled
bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select bits for PWM Generator #
(2,3)
These bits specify the Fault control source. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for available selections.
bit 2 FLTPOL: Fault Polarity bit for PWM Generator #(1)
1 = The selected fault source is active-low
0 = The selected fault source is active-high
bit 1-0 FLTMOD<1:0>: Fault Mode bits for PWM Generator #(4)
11 = Fault input is disabled
10 = Reserved
01 = The selected fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle)
00 = The selected fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition)
Note 1: These bits should be changed only when PTEN = 0. Changing the polarity selection during operation will
yield unpredictable results.
2: When Independent Fault mode is enabled (IFLTMOD = 1) and Fault 1 is used for Fault mode
(FLTSRC<4:0> = b0000), the Current-Limit Control Source Select bits (CLSRC<4:0>) should be set to an
unused current-limit source to prevent the current-limit source from disabling both the PWMxH and
PWMxL outputs.
3: When Independent Fault mode is enabled (IFLTMOD = 1), and Fault 1 is used for Current-Limit mode
(CLSRC<4:0> = b0000), the Fault Control Source Select bits (FLTSRC<4:0>) should be set to an unused
fault source to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs.
4: This feature is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific device
data sheet for availability.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-17
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-15: PDCx: PWM Generator Duty Cycle Register(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDCx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PDCx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PDCx<15:0>: PWM Generator # Duty Cycle Value bits
Note 1: In Independent PWM mode, PMOD<1:0> (IOCONx<11:10>) = 11, the PDCx register controls the PWMxH
duty cycle only. In Complementary, Redundant and Push-Pull PWM modes (PMOD<1:0>
(IOCONx<11:0>) = 00 01, , or 10), the PDCx register controls the duty cycle of both the PWMxH and
PWMxL.
Register 14-16: PHASEx: PWM Primary Phase Shift Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASEx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASEx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PHASEx<15:0>: PWM Phase Shift Value or Independent Time Base Period bits for the PWM Generator
Note 1: If the ITB bit = 0 (PWMCONx<9>), the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00,
01 10, or ) PHASEx<15:0> = Phase shift value for PWMxH and PWMxL outputs
• True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11) PHASEx<15:0> = Phase
shift value for PWMxH only
2: If the ITB bit = 1(PWMCONx<9>), the following applies based on the mode of operation:
• Complementary, Redundant, and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00,
01 10, or ) PHASEx<15:0> = Independent time base period value for PWMxH and PWMxL
• True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11) PHASEx<15:0> = Independent
time base period for PWMxH only
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-18 © 2010-2011 Microchip Technology Inc.
Register 14-17: SDCx: PWM Secondary Duty Cycle Register(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SDCx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SDCx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SDCx<15:0>: Secondary Duty Cycle bits for PWMxL output pin
Note 1: The SDCx register is used in Independent PWM mode only (PMOD<1:0> (IOCONx<11:10>) = 11. When
used in Independent PWM mode, the SDCx register controls the PWMxL duty cycle.
2: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
Register 14-18: SPHASEx: PWM Secondary Phase Shift Register
(1,2,3)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPHASEx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPHASEx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SPHASEx<15:0>: Secondary Phase Offset bits for PWMxL Output Pin
Note 1: If the ITB bit = 0 (PWMCONx<9>), the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00,
01 10, or ) SPHASEx<15:0> = Not used
• True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11) SPHASEx<15:0> = Phase
shift value for PWMxL only
2: If the ITB bit = 1 (PWMCONx<9>), the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00,
01 10, or ) SPHASEx<15:0> = Not used
• True Independent Output mode (PMOD<1:0> (IOCONx<11:10>) = 11) SPHASEx<15:0> =
Independent time base period value for PWMxL only
3: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific device
data sheet for availability.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-19
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-19: DTRx: PWM Dead Time Register
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DTRx<13:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DTRx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-0 DTRx<13:0>: Unsigned 14-bit Dead Time Value bits for PWMx Dead Time Unit
Register 14-20: ALTDTRx: PWM Alternate Dead Time Register
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — ALTDTRx<13:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ALTDTRx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13-0 ALTDTRx<13:0>: Unsigned 14-bit Dead Time Value bits for PWMx Dead Time Unit
Register 14-21: TRIGx: PWM Primary Trigger Compare Value Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRGCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRGCMP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TRGCMP<15:0>: Trigger Control Value bits
When the primary PWM functions in local time base, this register contains the compare values that
can trigger the ADC module.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-20 © 2010-2011 Microchip Technology Inc.
Register 14-22: TRGCONx: PWM Trigger Control Register
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
TRGDIV<3:0> — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — TRGSTRT<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits
1111 = Trigger output for every 16th trigger event
•
•
•
0010 = Trigger output for every 3rd trigger event
0001 = Trigger output for every 2nd trigger event
0000 = Trigger output for every trigger event
bit 11-6 Unimplemented: Read as ‘0’
bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits
111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled
•
•
•
000010 = Wait 2 PWM cycles before generating the first trigger event after the module is enabled
000001 = Wait 1 PWM cycles before generating the first trigger event after the module is enabled
000000 = Wait 0 PWM cycles before generating the first trigger event after the module is enabled
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-21
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-23: LEBCONx: Leading-Edge Blanking Control Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
PHR PHF PLR PLF FLTLEBEN CLLEBEN — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — BCH(1) BCL(1) BPHH BPHL BPLH BPLL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PHR: PWMxH Rising Edge Trigger Enable bit
1 = Rising edge of PWMxH will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores rising edge of PWMxH
bit 14 PHF: PWMxH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores falling edge of PWMxH
bit 13 PLR: PWMxL Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores rising edge of PWMxL
bit 12 PLF: PWMxL Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores falling edge of PWMxL
bit 11 FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected fault input
0 = Leading-Edge Blanking is not applied to selected fault input
bit 10 CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected current-limit input
0 = Leading-Edge Blanking is not applied to selected current-limit input
bit 9-6 Unimplemented: Read as ‘0’
bit 5 BCH: Blanking in Selected Blanking Signal High Enable bit(1)
1 = State blanking (of current-limit and/or fault input signals) when selected blanking signal is high
0 = No blanking when selected blanking signal is high
bit 4 BCL: Blanking in Selected Blanking Signal Low Enable bit
(1)
1 = State blanking (of current-limit and/or fault input signals) when selected blanking signal is low
0 = No blanking when selected blanking signal is low
bit 3 BPHH: Blanking in PWMxH High Enable bit
1 = State blanking (of current-limit and/or fault input signals) when PWMxH output is high
0 = No blanking when PWMxH output is high
bit 2 BPHL: Blanking in PWMxH Low Enable bit
1 = State blanking (of current-limit and/or fault input signals) when PWMxH output is low
0 = No blanking when PWMxH output is low
bit 1 BPLH: Blanking in PWMxL High Enable bit
1 = State blanking (of current-limit and/or fault input signals) when PWMxL output is high
0 = No blanking when PWMxL output is high
bit 0 BPLL: Blanking in PWMxL Low Enable bit
1 = State blanking (of current-limit and/or fault input signals) when PWMxL output is low
0 = No blanking when PWMxL output is low
Note 1: The blanking signal is selected via the BLANKSEL<3:0> bits (AUXCONx<11:8>).
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-22 © 2010-2011 Microchip Technology Inc.
Register 14-24: LEBDLYx: Leading-Edge Blanking Delay Register
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — LEB<11:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEB<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-0 LEB<11:0>: Leading-Edge Blanking Delay bits for Current-Limit and Fault Inputs
Register 14-25: PWMCAPx: Primary PWM Time Base Capture Register
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
PWMCAP<15:8>(1,2)
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
PWMCAP<7:0>(1,2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PWMCAP<15:0>: Captured PWM Time Base Value bits(1,2)
The value in this register represents the captured PWM time base value when a leading edge is
detected on the current-limit input.
Note 1: The capture feature is only available on the primary output (PWMxH).
2: The feature is only active after LEB processing on the current-limit input signal is complete.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-23
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-26: AUXCONx: PWM Auxiliary Control Register
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — BLANKSEL<3:0>(1)
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CHOPSEL<3:0>(1) CHOPHEN CHOPLEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 BLANKSEL<3:0>: PWM State Blank Source Select bits(1)
The selected state blank signal blocks the current-limit and/or fault input signals (if enabled via the
BCH and BCL bits in the LEBCONx register).
1111 = PWMxH selected as state blank source
•
•
•
0001 = PWMxH selected as state blank source
0000 = No state blanking
bit 7-6 Unimplemented: Read as ‘0’
bit 5-2 CHOPSEL<3:0>: PWM Chop Clock Source Select bits(1)
The selected signal will enable and disable (CHOP) the selected PWM outputs.
1111 = PWMxH selected as CHOP clock source
•
•
•
0001 = PWMxH selected as CHOP clock source
0000 = Chop clock generator selected as CHOP clock source
bit 1 CHOPHEN: PWMxH Output Chopping Enable bit
1 = PWMxH chopping function is enabled
0 = PWMxH chopping function is disabled
bit 0 CHOPLEN: PWMxL Output Chopping Enable bit
1 = PWMxL chopping function is enabled
0 = PWMxL chopping function is disabled
Note 1: These bit selections are device dependent. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-24 © 2010-2011 Microchip Technology Inc.
14.4 ARCHITECTURE OVERVIEW
Figure 14-1 illustrates the architectural overview of the High-Speed PWM module and its
interconnection with the CPU and other peripherals.
Figure 14-1: High-Speed PWM Module Architectural Overview(1)
CPU
Primary and Secondary
PWM
Generator 1
PWM
Generator 2
PWM
Generator x
PWM
Generator x
SYNCIx
SYNCOx
PWM1H
PWM1L
PWM1 Interrupt
PWM2H
PWM2L
PWM2 Interrupt
PWMxH
PWMxL
PWMx Interrupt
PWMxH
PWMxL
PWMx Interrupt
Synchronization Signal
Data Bus
ADC Module
FLTx and
Synchronization Signal
Synchronization Signal
Synchronization Signal
Primary Trigger
Primary Special
DTCMPx
Secondary Special
Event Trigger
Event Trigger Fault, Current-Limit
and Dead-Time Compensation
Master Time Base
Fault, Current-Limit
and Dead-Time Compensation
Fault, Current-Limit
and Dead-Time Compensation
Fault, Current-Limit
and Dead-Time Compensation
Note 1: Not all of the features and registers listed in this block diagram are available on all devices. Refer to the
“High-Speed PWM” chapter of the specific device data sheet for availability.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-26 © 2010-2011 Microchip Technology Inc.
Figure 14-2: High-Speed PWM Module Register Interconnection Diagram
MUX
PTMRx
PDCx
PWMCONx TRGCONx
PTCON, PTCON2
IOCONx
DTRx
PWMxL
PWMxH
FLTx
PWM1L
PWM1H
FCLCONx
MDC
PHASEx
LEBCONx
MUX
STMRx
SDCx
SPHASEx ALTDTRx
PWMCAPx
User Override Logic
Current-Limit
PWM Output Mode
Control Logic
Dead
Logic
Pin
Control
Logic
Fault and
Current-Limit
Logic
PWM Generator 1
FLTx
PWM Generator x
Interrupt
Logic
ADC Trigger
Module Control and Timing
Master Duty Cycle Register
Synchronization Synchronization
Master PeriodMaster Period
Master Duty CycleMaster Duty Cycle
Secondary PWM
SYNCI2
SYNCI1
SYNCO1
SEVTCMP
Comparator Special Event Trigger
Special Event
Postscaler
PTPER
PMTMR Primary Master Time Base
Master Time Base Counter
Special Event Compare Trigger
Comparator
Clock
Prescaler
Comparator
Comparator
Comparator
16-bit Data Bus
Time
TRIGx Fault Override Logic
Override Logic
SYNCO2
SEVTCMP
Comparator Special Event Trigger
Special Event
Postscaler
PTPER
PMTMR Secondary Master Time Base
Master Time Base Counter
Special Event Compare Trigger
Comparator
Clock
Prescaler
DTCMPx
DTCMP1
Note 1: Not all of the features and registers listed in this block diagram are available on all devices. Refer to the
“High-Speed PWM” chapter of the specific device data sheet for availability.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-27
Section 14. High-Speed PWM
High-Speed PWM
14
14.5 MODULE DESCRIPTION
14.5.1 PWM Clock Selection
The system clock is used to generate the clock for the High-Speed PWM module internally. The
maximum time resolution for this module is TOSC.
14.5.2 Time Base
Each PWM output in a PWM generator can use the master time base or an independent time
base. The input clock of the High-Speed PWM module has prescaler (divider) options of 1:1 to
1:64, which can be selected using the PWM Input Clock Prescaler (Divider) Select bits
(PCLKDIV<2:0>) in the PWM Clock Divider Select register (PTCON2<2:0>). The prescaled value
will also reflect the PWM resolution, which helps to reduce the power consumption of the
High-Speed PWM module. The prescaled clock is the input to the PWM clock control logic block.
The maximum clock rate provides a duty cycle and period resolution of TOSC.
For example:
• If a prescaler option of tion can be set 1:2 is selected, the PWM duty cycle and period resolu
at TOSC * 2. Thereby, the power consumption of the High-Speed PWM module would be
reduced by approximately 50 percent of the maximum speed operation.
• If a prescaler option of tion can be set 1:4 is selected, the PWM duty cycle and period resolu
at TOSC * 4. Thereby, the power consumption of the High-Speed PWM module would be
reduced by approximately 75 percent of the maximum speed operation.
The High-Speed PWM module can operate in the standard edge-aligned or center-aligned time
base.
14.5.3 Write Protection
Certain devices incorporate a write protection feature for the IOCONx and FCLCONx registers,
which prevents any inadvertent writes to these registers. This feature can be controlled by the
PWMLOCK Configuration bit (FOSCSEL<6>). The default state of the write protection feature is
enabled (PWMLOCK = 1). Refer to the “Special Features” chapter of the specific device data
sheet for more information of the Flash Configuration bytes.
To gain write access to the locked registers, the user application must write two consecutive
values of 0xABCD and 0x4321 to the PWMKEY register. The write access to the IOCONx or
FCLCONx registers must be the next SFR access following the unlock sequence; there can be
no other SFR accesses during the unlock process and subsequent write access. To write to both
the IOCONx and FCLCONx registers requires two unlock operations.
The correct unlocking sequence is described in Example 14-1.
Example 14-1: PWM Write-Protected Register Unlock Sequence
; FLT32 pin must be pulled high externally to clear and disable the fault
; Writing to FCLCON1 register requires unlock sequence
mov #0xabcd,w10 ;Load first unlock key to w10 register
mov #0x4321,w11 ;Load second unlock key to w11 register
mov #0x0000,w0 ;Load desired value of FCLCON1 register in w0
mov w10, PWMKEY ;Write first unlock key to PWMKEY register
mov w11, PWMKEY ;Write second unlock key to PWMKEY register
mov w0,FCLCON1 ;Write desired value to FCLCON1 register
; Set PWM ownership and polarity using the IOCON1 register
; Writing to IOCON1 register requires unlock sequence
mov #0xabcd,w10 ;Load first unlock key to w10 register
mov #0x4321,w11 ;Load second unlock key to w11 register
mov #0xF000,w0 ;Load desired value of IOCON1 register in w0
mov w10, PWMKEY ;Write first unlock key to PWMKEY register
mov w11, PWMKEY ;Write second unlock key to PWMKEY register
mov w0,IOCON1 ;Write desired value to IOCON1 register
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-30 © 2010-2011 Microchip Technology Inc.
14.5.6 Master Time Base/Synchronous Time Base
Figure 14-5 illustrates the PWM functionality in the master time base.
Figure 14-5: Master Time Base Block Diagram
Some of the common tasks of the master time base are as follows:
• Generates time reference for all the PWM generators
• Generates special event ADC trigger and interrupt
• Supports synchronization with the external SYNC signal (SYNCIx)
• Supports synchronization with external devices using SYNCOx signal
The master time base for a PWM generator is set by loading a 16-bit value into the Primary
Master Time Base Period register (PTPER). In Master Time Base mode, the value in the
PHASEx and SPHASEx registers provides phase shift between the PWM outputs.
The clock for
the PWM timer (PMTMR) is derived from the system clock.
14.5.7 Time Base Synchronization
The master time base can be synchronized with the external synchronization signal via the
master time base synchronization signal (SYNCIx). The synchronization source (SYNCIx) can
be selected using the SYNCSRC<1:0> bits (PTCON<5:4>). The SYNCPOL bit (PTCON<9>)
selects the rising or falling edge of the synchronization pulse, which resets the timer (PMTMR).
The external synchronization feature can be enabled or disabled with the SYNCEN bit
(PTCON<7>). The pulse-width of the external synchronization signal (SYNCIx) must be more
than the period of the post-scaled input clock to ensure reliable detection by the master time
base.
M
U
X
SYNCSRC
PMTMR
SEVTCMP
1:1
1:16
PTPER
SEVTPS
Reset
SYNCEN
SYNCI1
SYNCI2
SYNCOEN
SYNCO
Edge Detector
SYNCPOL
Special Event
Trigger to ADC
Synchronization Signal
PWM Clock
CMP
CMP
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-33
Section 14. High-Speed PWM
High-Speed PWM
14
14.6 PWM OPERATING MODES
The High-Speed PWM module supports the following operation modes:
• Push-Pull Output mode
• Complementary Output mode
• Redundant Output mode
• Independent Output mode (this feature is not available on all devices)
These operating modes can be selected using the PMOD<1:0> bits (IOCONx<11:10>).
In the following sections, figures and examples are provided, which show the PWM outputs in
multiple operating modes. Table 14-1 provides a list of the available modes and settings, with
references to the figures by number.
Table 14-1: Mode and Code Cross-reference Table
PWM Mode Mode Settings Related
Figure
Push-Pull Independent Duty Cycle and Phase, Fixed Primary Period, Edge-Aligned 14-7
Independent Duty Cycle and Phase, Fixed Secondary Period, Edge-Aligned 14-8
Master Duty Cycle and Independent Phase, Fixed Primary Period, Edge-Aligned 14-9
Master Duty Cycle and Independent Phase, Fixed Secondary Period, Edge-Aligned 14-10
Independent Duty Cycles and Periods, No Phase-Shifting, Edge-Aligned 14-11
Master Duty Cycles and Independent Periods, No Phase-Shifting, Edge-Aligned 14-12
Independent Duty Cycles and Periods, No Phase-Shifting, Center-Aligned Mode 14-13
Master Duty Cycles and Independent Periods, No Phase-Shifting, Center-Aligned Mode 14-14
Complementary Independent Duty Cycle and Phase, Fixed Primary Period, Edge-Aligned 14-15
Independent Duty Cycle and Phase, Fixed Secondary Period, Edge-Aligned 14-16
Master Duty Cycle and Independent Phase, Fixed Primary Period, Edge-Aligned 14-17
Master Duty Cycle and Independent Phase, Fixed Secondary Period, Edge-Aligned 14-18
Independent Duty Cycles and Periods, No Phase-Shifting, Edge-Aligned 14-19
Master Duty Cycles and Independent Periods, No Phase-Shifting, Edge-Aligned 14-20
Independent Duty Cycles and Periods, No Phase-Shifting, Center-Aligned 14-21
Master Duty Cycles and Independent Periods, No Phase-Shifting, Center-Aligned 14-22
Redundant Independent Duty Cycle and Phase, Fixed Primary Period, Edge-Aligned 14-23
Independent Duty Cycle and Phase, Fixed Secondary Period, Edge-Aligned 14-24
Master Duty Cycle and Variable Phase, Fixed Primary Period, Edge-Aligned 14-25
Master Duty Cycle and Variable Phase, Fixed Secondary Period, Edge-Aligned 14-26
Independent Duty Cycles and Periods, No Phase-Shifting, Edge-Aligned 14-27
Master Duty Cycles and Independent Periods, No Phase-Shifting, Edge-Aligned 14-28
Independent Duty Cycles and Periods, No Phase-Shifting, Center-Aligned 14-29
Master Duty Cycles and Independent Periods, No Phase-Shifting, Center-Aligned 14-30
Independent Independent Duty Cycle and Phase, Fixed Primary Period, Edge-Aligned 14-31
Independent Duty Cycle and Phase, Fixed Secondary Period, Edge-Aligned 14-32
Master Duty Cycle, Variable Phase, Fixed Primary Period, Edge-Aligned 14-33
Master Duty Cycle, Variable Phase, Fixed Secondary Period, Edge-Aligned 14-34
Independent Duty Cycles and Periods, No Phase-Shifting, Edge-Aligned 14-35
Master Duty Cycles, Independent Periods, No Phase-Shifting, Edge-Aligned 14-36
Independent Duty Cycles and Periods, No Phase-Shifting, Center-Aligned 14-37
Master Duty Cycles, Independent Periods, No Phase-Shifting, Center-Aligned 14-38
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-34 © 2010-2011 Microchip Technology Inc.
14.6.1 Push-Pull PWM Mode
In Push-Pull mode, the PWM outputs are alternately available on the PWMxH and PWMxL pins.
Some typical applications of Push-Pull mode are provided in 14.16 “Application Information”.
Figure 14-7 through Figure 14-14 and Example 14-6 through Example 14-13 show the PWM
outputs for Push-Pull PWM mode in multiple operating modes.
Figure 14-7: Push-Pull PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Note: Not all of the features and registers listed in the Figures and Code Examples in this
section are available on all devices. Refer to the “High-Speed PWM” chapter of the
specific device data sheet for availability.
PTPER
PHASE1 = 0
PHASE2
PHASE3
PDC1
Where:
PHASEx Phase of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
PTPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
PDC1
PDC2
PDC2
PDC3
PDC3
Complete
PWM1L Cycle
DTR1
ALTDTR1
ALTDTR2
DTR2
ALTDTR3
DTR3
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-35
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-6: Push-Pull PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-8: Push-Pull PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base */
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
PDC1 = 150;
PDC2 = 200;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Primary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0000;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
Where:
PHASEx Phase of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
STPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
STPER
PHASE1 = 0
PHASE2
PHASE3
PDC1
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
PDC1
PDC2
PDC2
PDC3
PDC3
Complete
PWM1L Cycle
DTR1
ALTDTR1
ALTDTR2
DTR2
ALTDTR3
DTR3
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-36 © 2010-2011 Microchip Technology Inc.
Example 14-7: Push-Pull PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
Figure 14-9: Push-Pull PWM Mode – Master Duty Cycle and Independent Phase, Fixed Primary Period,
Edge-Aligned
/* Set PWM Period on Secondary Time Base */
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
PDC1 = 150;
PDC2 = 200;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Secondary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0008;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
Where:
PHASEx Phase of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
PTPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
PTPER
PHASE1 = 0
PHASE2
PHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
MDC
MDC
MDC
MDC
MDC
Complete
PWM1L Cycle
DTR1
ALTDTR1
ALTDTR2
DTR2
ALTDTR3
DTR3
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-37
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-8: Push-Pull PWM Mode – Master Duty Cycle and Independent Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-10: Push-Pull PWM Mode – Master Duty Cycle and Independent Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base*/
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Primary Time Base, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0100;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
Where:
PHASEx Phase of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
STPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
STPER
PHASE1 = 0
PHASE2
PHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
MDC
MDC
MDC
MDC
MDC
Complete
PWM1L Cycle
DTR1
ALTDTR1
ALTDTR2
DTR2
ALTDTR3
DTR3
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-38 © 2010-2011 Microchip Technology Inc.
Example 14-9: Push-Pull PWM Mode – Master Duty Cycle and Independent Phase, Fixed Secondary Period,
Edge-Aligned
Figure 14-11: Push-Pull PWM Mode – Independent Duty Cycles and Independent Periods, No Phase-Shifting,
Edge-Aligned
/* Set PWM Period on Secondary Time Base*/
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Secondary Time Base, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0108;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
PDC1
PDC2
PDC3
PHASE1
PHASE2
PHASE3
Start of
PWM Cycle Complete
PWM1L Cycle
Where:
PHASEx Period of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
DTRx Dead time for PWMxH Rising Edge
ALTDTRx Dead time for PWMxL Rising Edge
ALTDTR3
ALTDTR2
ALTDTR1 DTR1
DTR2
DTR3
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-39
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-10: Push-Pull PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Edge-Aligned
Figure 14-12: Push-Pull PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Edge-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1000;
PHASE2 = 900;
PHASE3 = 800;
/* Set Duty Cycles */
PDC1 = 200;
PDC2 = 300;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Independent Time Bases, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0200;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
PHASE1
PHASE2
PHASE3
Start of
PWM Cycle Complete
PWM1L Cycle
Where:
PHASEx Period of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
ALTDTR3
ALTDTR2
ALTDTR1 DTR1
DTR2
DTR3

Termékspecifikációk

Márka: Microchip
Kategória: nincs kategorizálva
Modell: DSPIC33EP64MC204

Szüksége van segítségre?

Ha segítségre van szüksége Microchip DSPIC33EP64MC204, tegyen fel kérdést alább, és más felhasználók válaszolnak Önnek


Útmutatók nincs kategorizálva Microchip

Microchip

Microchip AT89C51AC2 Útmutató

15 Január 2025
Microchip

Microchip AT91SAM7S32 Útmutató

15 Január 2025
Microchip

Microchip AT91SAM7SE32 Útmutató

15 Január 2025
Microchip

Microchip AT89LS52 Útmutató

15 Január 2025
Microchip

Microchip AT91SAM7S512 Útmutató

15 Január 2025
Microchip

Microchip AT97SC3205T Útmutató

15 Január 2025
Microchip

Microchip AT91SAM7SE512 Útmutató

15 Január 2025
Microchip

Microchip AT91SAM9CN11 Útmutató

15 Január 2025
Microchip

Microchip ATECC608A-TFLXTLS Útmutató

15 Január 2025
Microchip

Microchip ATA8215 Útmutató

15 Január 2025

Útmutatók nincs kategorizálva

Legújabb útmutatók nincs kategorizálva

Planet

Planet PWR-240-48 Útmutató

9 Április 2025
CaterChef

CaterChef 445001 Útmutató

9 Április 2025
IFM

IFM E40581 Útmutató

9 Április 2025
Livn

Livn Bolt Útmutató

9 Április 2025
Livn

Livn Beats Útmutató

9 Április 2025
Alpine

Alpine DP2-40C-BC Útmutató

9 Április 2025
IFM

IFM O3R252 Útmutató

9 Április 2025
IFM

IFM PG1704 Útmutató

9 Április 2025
Daikin

Daikin EKWCTRDI1V3 Útmutató

9 Április 2025
Simplified MFG

Simplified MFG SP18CAT120 Útmutató

9 Április 2025