Használati útmutató Microchip dsPIC33CK256MP505 (131 oldal)

HRPWM with Fine Edge

Placement

dsPIC33/PIC24 Family Reference Manual

Introduction

Note: This family reference manual section is meant to serve as a complement to device data sheets. Depending on

the device variant, this manual section may not apply to all dsPIC33 devices. Please consult the note at the

beginning of the chapter in the specific device data sheet to check whether this document supports the device you

are using.

Device data sheets and family reference manual sections are available for download from the Microchip Worldwide

Website at: www.microchip.com.

This document describes the features and use of the High-Resolution Pulse-Width Modulated (PWM) with Fine Edge

Placement. This flexible module provides features to support many types of Motor Control (MC) and Power Control

(PC) applications, including:

• AC-to-DC Converters

• DC-to-DC Converters

• AC and DC Motor Control: Brushed DC, BLDC, PMSM, ACIM, SRM, Stepper, etc.

• Inverters

• Battery Chargers

• Digital Lighting

• Power Factor Correction (PFC)

High-Level Features

• Up to Eight Independent PWM Generators, each with Dual Outputs

• Operating modes:

– Independent Edge PWM mode

– Variable Phase PWM mode

– Independent Edge PWM mode, Dual Output

– Center-Aligned PWM mode

– Double Update Center-Aligned PWM mode

– Dual Edge Center-Aligned PWM mode

• Output modes:

– Complementary

– Independent

– Push-Pull

• Dead-Time Generator

• Dead-Time Compensation

• Leading-Edge Blanking (LEB)

• Output Override for Fault Handling

• Flexible Period/Duty Cycle Updating Options

• PWM Control Inputs (PCI) for PWM Pin Overrides and External PWM Synchronization

• Advanced Triggering Options

• Combinatorial Logic Output

• PWM Event Outputs

HRPWM with Fine Edge Placement

Table of Contents

Introduction.....................................................................................................................................................1

High-Level Features....................................................................................................................................... 1

1. Registers................................................................................................................................................. 5

2. Register Maps......................................................................................................................................... 6

2.1. Common Functions Register Map................................................................................................7

2.2. PWM Generator Register Map................................................................................................... 21

3. Architecture Overview...........................................................................................................................51

4. Operation.............................................................................................................................................. 54

4.1. PWM Clocking............................................................................................................................54

4.2. PWM Generator (PG) Features..................................................................................................59

4.3. Common Features......................................................................................................................95

4.4. Lock and Write Restrictions......................................................................................................100

5. Application Examples..........................................................................................................................105

5.1. Six-Step Commutation of Three-Phase BLDC Motor...............................................................105

5.2. Three-Phase Sinusoidal Control of PMSM/ACIM Motors.........................................................114

5.3. Simple Complementary PWM Output.......................................................................................117

5.4. Cycle-by-Cycle Current Limit Mode..........................................................................................118

5.5. External Period Reset Mode.................................................................................................... 120

6. Interrupts............................................................................................................................................. 123

7. Operation in Power-Saving Modes..................................................................................................... 124

7.1. Operation in Sleep Mode..........................................................................................................124

7.2. Operation in Idle Mode............................................................................................................. 124

8. Related Application Notes...................................................................................................................125

9. Revision History.................................................................................................................................. 126

9.1. Revision A (August 2017).........................................................................................................126

9.2. Revision B (February 2018)..................................................................................................... 126

9.3. Revision C (February 2019)..................................................................................................... 126

9.4. Revision D (December 2020)................................................................................................... 126

The Microchip Website...............................................................................................................................128

Product Change Notification Service..........................................................................................................128

Customer Support...................................................................................................................................... 128

Microchip Devices Code Protection Feature..............................................................................................128

Legal Notice............................................................................................................................................... 129

Trademarks................................................................................................................................................ 129

Quality Management System..................................................................................................................... 130

HRPWM with Fine Edge Placement

Worldwide Sales and Service.....................................................................................................................131

HRPWM with Fine Edge Placement

1. Registers

There are two categories of Special Function Registers (SFRs) used to control the operation of the PWM module:

• Common, shared by all PWM Generators

• PWM Generator-specific

An ‘x’ in the register name denotes an instance of a PWM Generator.

A ‘y’ in the register name denotes an instance of a common function.

The LOCK bit in the PCLKCON register may be set in software to block writes to certain registers and bits. See 4.2

PWM Generator (PG) Features for more information. Writes to certain data and control registers are not safe at

certain times of a PWM cycle or when the module is enabled.

HRPWM with Fine Edge Placement

Registers

2. Register Maps

Section provides a brief summary of the related common High-Resolution2.1 Common Functions Register Map

PWM with Fine Edge Placement registers. Section provides a brief summary of2.2 PWM Generator Register Map

the PWM Generator registers. The corresponding registers appear after the summaries, followed by a detailed

description of each register.

HRPWM with Fine Edge Placement

Register Maps

2.1 Common Functions Register Map

Note: The number of LOGCONy and PWMEVTy registers are device-dependent. Refer to the device data sheet for

availability.

Name Bit Pos. 7 6 5 4 3 2 1 0

PCLKCON 7:0 DIVSEL[1:0] MCLKSEL[1:0]

15:8 HRRDY HRERR LOCK

FSCL 7:0 FSCL[7:0]

15:8 FSCL[15:8]

FSMINPER 7:0 FSMINPER[7:0]

15:8 FSMINPER[15:8]

MPHASE 7:0 MPHASE[7:0]

15:8 MPHASE[15:8]

MDC 7:0 MDC[7:0]

15:8 MDC[15:8]

MPER 7:0 MPER[7:0]

15:8 MPER[15:8]

LFSR 7:0 LFSR[7:0]

15:8 LFSR[14:8]

CMBTRIGL 7:0 CTA8EN CTA7EN CTA6EN CTA5EN CTA4EN CTA3EN CTA2EN CTA1EN

15:8

CMBTRIGH 7:0 CTB8EN CTB7EN CTB6EN CTB5EN CTB4EN CTB3EN CTB2EN CTB1EN

15:8

LOGCONy 7:0 S1yPOL S2yPOL PWMLFy[1:0] PWMLFyD[2:0]

15:8 PWMS1y[3:0] PWMS2y[3:0]

PWMEVTy 7:0 EVTySEL[3:0] EVTyPGS[2:0]

15:8 EVTyOEN EVTyPOL EVTySTRD EVTySYNC

HRPWM with Fine Edge Placement

Register Maps

2.1.1 PWM Clock Control Register

Name: PCLKCON

Legend: C = Clearable bit

Bit 15 14 13 12 11 10 9 8

HRRDY HRERR LOCK

Access R R/C R/W

Reset 0 0 0

Bit 7 6 5 4 3 2 1 0

DIVSEL[1:0] MCLKSEL[1:0]

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 15 – HRRDY High-Resolution Ready

Note: This bit is not present on all devices. Refer to the device-specific data sheet for availability.

Value Description

1The high-resolution circuitry is ready

0The high-resolution circuitry is not ready

Bit 14 – HRERR High-Resolution Error(1,2)

Notes:

1. This bit is not present on all devices. Refer to the device-specific data sheet for availability.

2. User software may write a ‘ ’ to this location to request a reset of the High-Resolution block when HRRDY = .0 1

Value Description

1An error has occurred; PWM signals will have limited resolution

0No error has occurred; PWM signals will have full resolution when HRRDY = 1

Bit 8 – LOCK Lock

Note: A device-specific unlock sequence must be performed before this bit can be cleared. Refer to the device data

sheet for the unlock sequence.

Value Description

1Write-protected registers and bits are locked

0Write-protected registers and bits are unlocked

Bits 5:4 – DIVSEL[1:0] PWM Clock Divider Selection

Value Description

11 Divide ratio is 1:16

10 Divide ratio is 1:8

01 Divide ratio is 1:4

00 Divide ratio is 1:2

Bits 1:0 – MCLKSEL[1:0] PWM Master Clock Selection

Clock sources are device-specific. Refer to the device data sheet for selections.

Note: Do not change the MCLKSEL[1:0] bits while ON (PGxCONL[15]) = .1

HRPWM with Fine Edge Placement

Register Maps

2.1.2 Frequency Scale Register

Name: FSCL

Bit 15 14 13 12 11 10 9 8

FSCL[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

FSCL[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – FSCL[15:0] Frequency Scale Register

The value in this register is added to the frequency scaling accumulator at each pwm_master_clk. When the

accumulated value exceeds the value of FSMINPER, a clock pulse is produced.

HRPWM with Fine Edge Placement

Register Maps

2.1.3 Frequency Scaling Minimum Period Register

Name: FSMINPER

Bit 15 14 13 12 11 10 9 8

FSMINPER[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

FSMINPER[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – FSMINPER[15:0] Frequency Scaling Minimum Period Register

This register holds the minimum clock period (maximum clock frequency) that can be produced by the frequency

scaling circuit.

HRPWM with Fine Edge Placement

Register Maps

2.1.5 Master Duty Cycle Register

Name: MDC

Bit 15 14 13 12 11 10 9 8

MDC[15:8]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

MDC[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – MDC[15:0] Master Duty Cycle Register

This register holds the duty cycle value that can be shared by multiple PWM Generators.

Note: Duty cycle values less than 0x0008 should not be used (0x0020 in High-Resolution mode).

HRPWM with Fine Edge Placement

Register Maps

2.1.7 Linear Feedback Shift Register

Name: LFSR

Bit 15 14 13 12 11 10 9 8

LFSR[14:8]

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

LFSR[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 14:0 – LFSR[14:0] Linear Feedback Shift Register

A read of this register will provide a 15-bit pseudorandom value.

HRPWM with Fine Edge Placement

Register Maps

2.1.8 Combinational Trigger Register Low

Name: CMBTRIGL

Bit 15 14 13 12 11 10 9 8

Access

Reset

Bit 7 6 5 4 3 2 1 0

CTA8EN CTA7EN CTA6EN CTA5EN CTA4EN CTA3EN CTA2EN CTA1EN

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 – CTA8EN Enable Trigger Output from PWM Generator #8 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 6 – CTA7EN Enable Trigger Output from PWM Generator #7 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 5 – CTA6EN Enable Trigger Output from PWM Generator #6 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 4 – CTA5EN Enable Trigger Output from PWM Generator #5 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 3 – CTA4EN Enable Trigger Output from PWM Generator #4 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 2 – CTA3EN Enable Trigger Output from PWM Generator #3 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 1 – CTA2EN Enable Trigger Output from PWM Generator #2 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

Bit 0 – CTA1EN Enable Trigger Output from PWM Generator #1 as Source for Combinational Trigger A

Value Description

1Enables specified trigger signal to be OR’d into the Combinatorial Trigger A signal

0Disabled

HRPWM with Fine Edge Placement

Register Maps

2.1.10 Combinatorial PWM Logic Control Register y

Name: LOGCONy

Note: ‘y’ denotes a common instance (A-F); the number of the available combinatorial PWM logic is device-

dependent. Refer to the device data sheet for availability.

Bit 15 14 13 12 11 10 9 8

PWMS1y[3:0] PWMS2y[3:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

S1yPOL S2yPOL PWMLFy[1:0] PWMLFyD[2:0]

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bits 15:12 – PWMS1y[3:0] Combinatorial PWM Logic Source #1 Selection

Note: Logic function input will be connected to ‘ ’ if the PWM channel is not present.0

Value Description

1111 PWM8L

1110 PWM8H

1101 PWM7L

1100 PWM7H

1011 PWM6L

1010 PWM6H

1001 PWM5L

1000 PWM5H

0111 PWM4L

0110 PWM4H

0101 PWM3L

0100 PWM3H

0011 PWM2L

0010 PWM2H

0001 PWM1L

0000 PWM1H

Bits 11:8 – PWMS2y[3:0] Combinatorial PWM Logic Source #2 Selection

Note: Logic function input will be connected to ‘ ’ if the PWM channel is not present.0

Value Description

1111 PWM8L

1110 PWM8H

1101 PWM7L

1100 PWM7H

1011 PWM6L

1010 PWM6H

1001 PWM5L

1000 PWM5H

0111 PWM4L

0110 PWM4H

0101 PWM3L

0100 PWM3H

0011 PWM2L

0010 PWM2H

0001 PWM1L

HRPWM with Fine Edge Placement

Register Maps

Value Description

0000 PWM1H

Bit 7 – S1yPOL Combinatorial PWM Logic Source #1 Polarity

Value Description

1Input is inverted

0Input is positive logic

Bit 6 – S2yPOL Combinatorial PWM Logic Source #2 Polarity

Value Description

1Input is inverted

0Input is positive logic

Bits 5:4 – PWMLFy[1:0] Combinatorial PWM Logic Function Selection

Value Description

11 Reserved

10 PWMS1y ^ PWMS2y (XOR)

01 PWMS1y & PWMS2y (AND)

00 PWMS1y | PWMS2y (OR)

Bits 2:0 – PWMLFyD[2:0] Combinatorial PWM Logic Destination Selection

Note: Instances of y = A, C, E of LOGCONy assign logic function output to the PWMxH pin. Instances of y = B, D, F

of LOGCONy assign logic function to the PWMxL pin.

Value Description

111 Logic function is assigned to PWM8

110 Logic function is assigned to PWM7

101 Logic function is assigned to PWM6

100 Logic function is assigned to PWM5

011 Logic function is assigned to PWM4

010 Logic function is assigned to PWM3

001 Logic function is assigned to PWM2

000 No assignment, combinatorial PWM logic function is disabled

HRPWM with Fine Edge Placement

Register Maps

2.1.11 PWM Event Output Control Register y

Name: PWMEVTy

Note: ‘y’ denotes a common instance (A-F); the number of the available combinatorial PWM logic is

device-dependent. Refer to the device data sheet for availability.

Bit 15 14 13 12 11 10 9 8

EVTyOEN EVTyPOL EVTySTRD EVTySYNC

Access R/W R/W R/W R/W

Reset 0 0 0 0

Bit 7 6 5 4 3 2 1 0

EVTySEL[3:0] EVTyPGS[2:0]

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bit 15 – EVTyOEN PWM Event Output Enable

Value Description

1Event output signal is output on the PWMEy pin

0Event output signal is internal only

Bit 14 – EVTyPOL PWM Event Output Polarity

Value Description

1Event output signal is active-low

0Event output signal is active-high

Bit 13 – EVTySTRD PWM Event Output Stretch Disable

Note: The event signal is stretched using peripheral_clk because different PWM Generators may be operating from

different clock sources.

Value Description

1Event output signal pulse width is not stretched

0Event output signal is stretched to eight PWM clock cycles minimum

Bit 12 – EVTySYNC PWM Event Output Sync

Event output signal pulse will be synchronized to peripheral_clk.

Value Description

1Event output signal is synchronized to the system clock

0Event output is not synchronized to the system clock

Bits 7:4 – EVTySEL[3:0] PWM Event Selection

Note: This is the PWM Generator output signal prior to Output mode logic and any output override logic.

Value Description

1111 High-resolution error event signal

1110-1010 Reserved

1001 ADC Trigger 2 signal

1000 ADC Trigger 1 signal

0111 STEER signal (available in Push-Pull Output modes only)

0110 CAHALF signal (available in Center-Aligned modes only)

0101 PCI Fault active output signal

0100 PCI current limit active output signal

0011 PCI feed-forward active output signal

0010 PCI Sync active output signal

0001 PWM Generator output signal

(1)

0000 Source is selected by the [2:0] bitsPGTRGSEL

HRPWM with Fine Edge Placement

Register Maps

Bits 2:0 – EVTyPGS[2:0] PWM Event Source Selection

Note: No event will be produced if the selected PWM Generator is not present.

Value Description

111 PWM Generator #8

110 PWM Generator #7

101 PWM Generator #6

100 PWM Generator #5

011 PWM Generator #4

010 PWM Generator #3

001 PWM Generator #2

000 PWM Generator #1

HRPWM with Fine Edge Placement

Register Maps

2.2 PWM Generator Register Map

Legend: x = PWM Generator #; y = F, CL, FF or S.

Name Bit Pos. 7 6 5 4 3 2 1 0

Reserved

PGxCONL 7:0 HREN CLKSEL[1:0] MODSEL[2:0]

15:8 ON TRGCNT[2:0]

PGxCONH 7:0 Reserved TRGMOD SOCS[3:0]

15:8 MDCSEL MPERSEL MPHSEL MSTEN UPDMOD[2:0]

PGxSTAT 7:0 TRSET TRCLR CAP UPDATE UPDREQ STEER CAHALF TRIG

15:8 SEVT FLTEVT CLEVT FFEVT SACT FLTACT CLACT FFACT

PGxIOCONL 7:0 FLTDAT[1:0] CLDAT[1:0] FFDAT[1:0] DBDAT[1:0]

15:8 CLMOD SWAP OVRENH OVRENL OVRDAT[1:0] OSYNC[1:0]

PGxIOCONH 7:0 PMOD[1:0] PENH PENL POLH POLL

15:8 CAPSRC[2:0] DTCMPSEL

PGxEVTL 7:0 UPDTRG[1:0] PGTRGSEL[2:0]

15:8 ADTR1PS[4:0] ADTR1EN3 ADTR1EN2 ADTR1EN1

PGxEVTH 7:0 ADTR2EN3 ADTR2EN2 ADTR2EN1 ADTR1OFS[4:0]

15:8 FLTIEN CLIEN FFIEN SIEN IEVTSEL[1:0]

PGxyPCIL 7:0 SWTERM PSYNC PPS PSS[4:0]

15:8 TSYNCDIS TERM[2:0] AQPS AQSS[2:0]

PGxyPCIH 7:0 SWPCI SWPCIM[1:0] LATMOD TQPS TQSS[2:0]

15:8 BPEN BPSEL[2:0] ACP[2:0]

Reserved

PGxLEBL 7:0 LEB[10:6] [2:0]

15:8 LEB[18:11]

PGxLEBH 7:0 PHR PHF PLR PLF

15:8 PWMPCI[2:0]

PGxPHASE 7:0 PGxPHASE[7:0]

15:8 PGxPHASE[15:8]

Reserved

PGxDC 7:0 PGxDC[7:0]

15:8 PGxDC[15:8]

PGxDCA 7:0 PGxDCA[7:0]

15:8

PGxPER 7:0 PGxPER[7:0]

15:8 PGxPER[15:8]

PGxTRIGA 7:0 PGxTRIGA[7:0]

15:8 PGxTRIGA[15:8]

PGxTRIGB 7:0 PGxTRIGB[7:0]

15:8 PGxTRIGB[15:8]

PGxTRIGC 7:0 PGxTRIGC[7:0]

15:8 PGxTRIGC[15:8]

PGxDTL 7:0 DTL[7:0]

15:8 DTL[13:8]

PGxDTH 7:0 DTH[7:0]

15:8 DTH[13:8]

PGxCAP 7:0 PGxCAP[6:0]

15:8 PGxCAP[14:7]

HRPWM with Fine Edge Placement

Register Maps

Value Description

100 Center-Aligned PWM mode

011 Reserved

010 Independent Edge PWM mode, dual output

001 Variable Phase PWM mode

000 Independent Edge PWM mode

HRPWM with Fine Edge Placement

Register Maps

2.2.2 PWM Generator x Control Register High

Name: PGxCONH

Bit 15 14 13 12 11 10 9 8

MDCSEL MPERSEL MPHSEL MSTEN UPDMOD[2:0]

Access R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

Reserved TRGMOD SOCS[3:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 15 – MDCSEL Master Duty Cycle Register Select

Value Description

1PWM Generator uses MDC register

0PWM Generator uses PGxDC register

Bit 14 – MPERSEL Master Period Register Select

Value Description

1PWM Generator uses MPER register

0PWM Generator uses PGxPER register

Bit 13 – MPHSEL Master Phase Register Select

Value Description

1PWM Generator uses MPHASE register

0PWM Generator uses PGxPHASE register

Bit 11 – MSTEN Master Update Enable

Value Description

1PWM Generator broadcasts software set of UPDREQ control bit and EOC signal to other PWM

Generators

0PWM Generator does not broadcast UPDREQ status bit state or EOC signal

Bits 10:8 – UPDMOD[2:0] PWM Buffer Update Mode Selection

See Table 4-5 for details.

Bit 7 – Reserved Maintain as ‘ ’0

Bit 6 – TRGMOD PWM Generator x Trigger Mode Selection

Value Description

1PWM Generator operates in Retriggerable mode

0PWM Generator operates in Single Trigger mode

Bits 3:0 – SOCS[3:0] Start-of-Cycle Selection bits(1,2,3)

Notes:

1. The PCI selected Sync signal is always available to be OR’d with the selected SOC signal per the SOCS[3:0]

bits if the PCI Sync function is enabled.

2. The source selected by the SOCS[3:0] bits MUST operate from the same clock source as the local PWM

Generator. If not, the source must be routed through the PCI Sync logic so the trigger signal may be

synchronized to the PWM Generator clock domain.

3. PWM Generators are grouped into groups of four: PG1-PG4 and PG5-PG8, if available. Any generator within

a group of four may be used to trigger another generator within the same group.

HRPWM with Fine Edge Placement

Register Maps

Bits 5:4 – CLDAT[1:0] Data for PWMxH/PWMxL Pins if CLMT Event is Active

Description

If current limit is active, then CLDAT[1] provides data for PWMxH.

If current limit is active, then CLDAT[0] provides data for PWMxL.

Bits 3:2 – FFDAT[1:0] Data for PWMxH/PWMxL Pins if Feed-Forward Event is Active

Description

If feed-forward is active, then FFDAT[1] provides data for PWMxH.

If feed-forward is active, then FFDAT[0] provides data for PWMxL.

Bits 1:0 – DBDAT[1:0] Data for PWMxH/PWMxL Pins if Debug Mode is Active

Description

If Debug mode is active and PTFRZ = , then DBDAT[1] provides data for PWMxH.1

If Debug mode is active and PTFRZ = , then DBDAT[0] provides data for PWMxL.1

HRPWM with Fine Edge Placement

Register Maps

Value Description

1Output pin is active-low

0Output pin is active-high

HRPWM with Fine Edge Placement

Register Maps

2.2.6 PWM Generator x Event Register Low

Name: PGxEVTL

Bit 15 14 13 12 11 10 9 8

ADTR1PS[4:0] ADTR1EN3 ADTR1EN2 ADTR1EN1

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

UPDTRG[1:0] PGTRGSEL[2:0]

Access R/W R/W R/W R/W R/W

Reset 0 0 0 0 0

Bits 15:11 – ADTR1PS[4:0] ADC Trigger 1 Postscaler Selection

Value Description

11111 1:32

. . . . . .

00010 1:3

00001 1:2

00000 1:1

Bit 10 – ADTR1EN3 ADC Trigger 1 Source is PGxTRIGC Compare Event Enable

Value Description

1PGxTRIGC register compare event is enabled as trigger source for ADC Trigger 1

0PGxTRIGC register compare event is disabled as trigger source for ADC Trigger 1

Bit 9 – ADTR1EN2 ADC Trigger 1 Source is PGxTRIGB Compare Event Enable

Value Description

1PGxTRIGB register compare event is enabled as trigger source for ADC Trigger 1

0PGxTRIGB register compare event is disabled as trigger source for ADC Trigger 1

Bit 8 – ADTR1EN1 ADC Trigger 1 Source is PGxTRIGA Compare Event Enable

Value Description

1PGxTRIGA register compare event is enabled as trigger source for ADC Trigger 1

0PGxTRIGA register compare event is disabled as trigger source for ADC Trigger 1

Bits 4:3 – UPDTRG[1:0] Update Trigger Select

Value Description

11 A write of the PGxTRIGA register automatically sets the UPDREQ bit

10 A write of the PGxPHASE register automatically sets the UPDREQ bit

01 A write of the PGxDC register automatically sets the UPDREQ bit

00 User must set the bit (PGxSTAT[3]) manuallyUPDREQ

Bits 2:0 – PGTRGSEL[2:0] PWM Generator Trigger Output Selection

Note: These events are derived from the internal PWM Generator time base comparison events.

Value Description

111 Reserved

110 Reserved

101 Reserved

100 Reserved

011 PGxTRIGC compare event is the PWM Generator trigger

010 PGxTRIGB compare event is the PWM Generator trigger

001 PGxTRIGA compare event is the PWM Generator trigger

000 EOC event is the PWM Generator trigger

HRPWM with Fine Edge Placement

Register Maps

2.2.7 PWM Generator x Event Register High

Name: PGxEVTH

Bit 15 14 13 12 11 10 9 8

FLTIEN CLIEN FFIEN SIEN IEVTSEL[1:0]

Access R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

ADTR2EN3 ADTR2EN2 ADTR2EN1 ADTR1OFS[4:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 15 – FLTIEN PCI Fault Interrupt Enable

Note: An interrupt is only generated on the rising edge of the PCI Fault active signal.

Value Description

1Fault interrupt is enabled

0Fault interrupt is disabled

Bit 14 – CLIEN PCI Current Limit Interrupt Enable

Note: An interrupt is only generated on the rising edge of the PCI current limit active signal.

Value Description

1Current limit interrupt is enabled

0Current limit interrupt is disabled

Bit 13 – FFIEN PCI Feed-Forward Interrupt Enable

Note: An interrupt is only generated on the rising edge of the PCI feed-forward active signal.

Value Description

1Feed-forward interrupt is enabled

0Feed-forward interrupt is disabled

Bit 12 – SIEN PCI Sync Interrupt Enable

Note: An interrupt is only generated on the rising edge of the PCI Sync active signal.

Value Description

1Sync interrupt is enabled

0Sync interrupt is disabled

Bits 9:8 – IEVTSEL[1:0] Interrupt Event Selection

Value Description

11 Time base interrupts are disabled (Sync, Fault, current limit and feed-forward events can be

independently enabled)

10 Interrupts CPU at ADC Trigger 1 event

01 Interrupts CPU at TRIGA compare event

00 Interrupts CPU at EOC

Bit 7 – ADTR2EN3 ADC Trigger 2 Source is PGxTRIGC Compare Event Enable

Value Description

1PGxTRIGC register compare event is enabled as trigger source for ADC Trigger 2

0PGxTRIGC register compare event is disabled as trigger source for ADC Trigger 2

Márka:	Microchip
Kategória:	nincs kategorizálva
Modell:	dsPIC33CK256MP505

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